HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 285

IC H8 MCU FLASH 128K 100QFP

HD64F3048F16

Manufacturer Part Number
HD64F3048F16
Description
IC H8 MCU FLASH 128K 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of HD64F3048F16

Core Processor
H8/300H
Core Size
16-Bit
Speed
8MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Package
100PQFP
Family Name
H8
Maximum Speed
16 MHz
Operating Supply Voltage
5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
70
Interface Type
SCI
On-chip Adc
8-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F3048F16
Manufacturer:
RENESAS
Quantity:
1
Part Number:
HD64F3048F16
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD64F3048F16
Manufacturer:
HIT
Quantity:
1 000
Part Number:
HD64F3048F16
Manufacturer:
RENESAS
Quantity:
20 000
Part Number:
HD64F3048F16V
Manufacturer:
SIEMENS
Quantity:
200
Part Number:
HD64F3048F16V
Manufacturer:
RENESAS
Quantity:
5 530
Part Number:
HD64F3048F16V
Manufacturer:
RENESAS
Quantity:
3 477
Part Number:
HD64F3048F16V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
8.6.8
When a transfer is aborted by clearing the DTE bit or suspended by an NMI that clears the DTME
bit, if this halts a channel for which the DMAC has a transfer request pending internally, a dead
cycle may occur. This dead cycle does not update the halted channel’s address register or counter
value. Figure 8.27 shows an example in which an auto-requested transfer in cycle-steal mode on
channel 0 is aborted by clearing the DTE bit in channel 0.
Address bus
RD
HWR, LWR
Bus Cycle when Transfer Is Aborted
Figure 8.27 Bus Timing at Abort of DMA Transfer in Cycle-Steal Mode
CPU cycle
T
1
T
2
T
d
T
1
DMAC cycle
T
2
T
1
T
2
Rev. 3.00 Sep 27, 2006 page 257 of 872
T
1
CPU cycle
DTE bit is
cleared
T
2
T
3
Section 8 DMA Controller
T
d
DMAC
cycle
T
d
REJ09B0325-0300
T
1
CPU cycle
T
2

Related parts for HD64F3048F16