HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 192

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 7 Refresh Controller
Bit 7—Self-Refresh Mode (SRFMD): Specifies DRAM or pseudo-static RAM self-refresh
during software standby mode. When PSRAME = 1 and DRAME = 0, after the SRFMD bit is set
to 1, pseudo-static RAM can be self-refreshed when the H8/3048B Group enters software standby
mode. When PSRAME = 0 and DRAME = 1, after the SRFMD bit is set to 1, DRAM can be self-
refreshed when the H8/3048B Group enters software standby mode. In either case, the normal
access state resumes on exit from software standby mode.
Bit 7: SRFMD
0
1
Bit 6—PSRAM Enable (PSRAME) and
Bit 5—DRAM Enable (DRAME): These bits enable or disable connection of pseudo-static RAM
and DRAM to area 3 of the external address space.
When DRAM or pseudo-static RAM is connected, the bus cycle and refresh cycle of area 3 consist
of three states, regardless of the setting in the access state control register (ASTCR). If AST3 = 0
in ASTCR, wait states cannot be inserted.
When the PSRAME or DRAME bit is set to 1, bits 0, 2, 3, and 4 in RFSHCR and registers
RTMCSR, RTCNT, and RTCOR are write-disabled, except that the CMF flag in RTMCSR can be
cleared by writing 0.
Bit 6: PSRAME
0
1
Bit 4—Strobe Mode Select (CAS/WE
valid when PSRAME = 0 and DRAME = 1. This bit is write-disabled when the PSRAME or
DRAME bit is set to 1.
Bit 4: CAS/WE
0
1
Rev. 3.00 Sep 27, 2006 page 164 of 872
REJ09B0325-0300
WE
WE
WE
DRAM or PSRAM self-refresh is disabled in software standby mode
DRAM or PSRAM self-refresh is enabled in software standby mode
0
1
0
1
Description
2WE mode
2CAS mode
Description
Bit 5: DRAME
WE): Selects 2CAS or 2WE mode. The setting of this bit is
WE
WE
Description
Can be used as an interval timer
(DRAM and PSRAM cannot be directly connected)
DRAM can be directly connected
PSRAM can be directly connected
Illegal setting
(Initial value)
(Initial value)
(Initial value)