HD64F3048F16 Renesas Electronics America, HD64F3048F16 Datasheet - Page 446

• Manufacturer Part Number: HD64F3048F16
• Description: IC H8 MCU FLASH 128K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3048F16

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Package: 100PQFP
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 70
• Interface Type: SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 11 Programmable Timing Pattern Controller
11.1.4
Table 11.2 summarizes the TPC registers.
Table 11.2 TPC Registers
Address *
H'FFD1
H'FFD3
H'FFD4
H'FFD6
H'FFA0
H'FFA1
H'FFA2
H'FFA3
H'FFA5/
H'FFA7 *
H'FFA4
H'FFA6 *
Notes: 1. Lower 16 bits of the address.
Rev. 3.00 Sep 27, 2006 page 418 of 872
REJ09B0325-0300
2. Bits used for TPC output cannot be written.
3. The NDRA address is H'FFA5 when the same output trigger is selected for TPC output
3
3
Registers
1
groups 0 and 1 by settings in TPCR. When the output triggers are different, the NDRA
address is H'FFA7 for group 0 and H'FFA5 for group 1. Similarly, the address of NDRB
is H'FFA4 when the same output trigger is selected for TPC output groups 2 and 3 by
settings in TPCR. When the output triggers are different, the NDRB address is H'FFA6
for group 2 and H'FFA4 for group 3.
Name
Port A data direction register
Port A data register
Port B data direction register
Port B data register
TPC output mode register
TPC output control register
Next data enable register B
Next data enable register A
Next data register A
Next data register B
PADR
PBDR
Abbreviation
PADDR
PBDDR
TPMR
TPCR
NDERB
NDERA
NDRA
NDRB
R/W
W
R/(W) *
W
R/(W) *
R/W
R/W
R/W
R/W
R/W
R/W
2
2
Initial Value
H'00
H'00
H'00
H'00
H'F0
H'FF
H'00
H'00
H'00
H'00