HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet
HD64F3337YCP16
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HD64F3337YCP16 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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H8/300 Programming Manual ...
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Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise ...
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The H8/300 CPU forms the common core of all chips in the H8/300 Series. Featuring a Hitachi-original, high-speed, RISC-like architecture, it has eight 16-bit (or sixteen 8-bit) general registers and a concise, optimized instruction set. This manual gives detailed descriptions ...
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Section 1. CPU................................................................................................... 1.1 General CPU Architecture............................................................................................... 2 1.2 Registers .......................................................................................................................... 5 1.3 Instructions ...................................................................................................................... 8 Section 2. Instruction Set ADD (ADD binary) (byte) .............................................................................................. 37 ADD (ADD binary) (word) ............................................................................................. 38 ADDS (ADD with Sign extension) ................................................................................. 39 ADDX ...
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INC (INCrement) ............................................................................................................ 78 JMP (JuMP)..................................................................................................................... 79 JSR (Jump to SubRoutine) .............................................................................................. 80 LDC (LoaD to Control register) ...................................................................................... 81 MOV(MOVe data) (byte)................................................................................................. 82 MOV(MOVe data) (word) ............................................................................................... 83 MOV(MOVe data) (byte)................................................................................................. 84 MOV(MOVe data) (word) ............................................................................................... 85 MOV(MOVe data) ...
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XORC (eXclusive OR Control register)..........................................................................116 Appendix A. Operation Code Map Appendix B. Instruction Set List Appendix C. Number of Execution States ..............................................................................117 ..................................................................................118 .................................................................124 ...
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This document is a reference manual for programming the H8/300, a high-speed central processing unit with a Hitachi-original RISC-like architecture that is employed as a CPU core in a series of low-cost single-chip microcomputers intended for applications ranging from smart ...
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General CPU Architecture 1.1.1 Features Table 1-1 summarizes the CPU architecture. Figures 1-1 and 1-2 show how data are stored in registers and memory. Table 1-1. CPU Architecture Item Description Address space 64K bytes, H'0000 to H'FFFF Data types ...
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The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in packed BCD form. Each 4-bit of the byte is treated as a decimal digit. • The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits DIVXU ...
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Memory Data Structure: Figure 1-2 indicates the data structure in memory. Word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as “0.” odd ...
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Registers Figure 1-3 shows the register structure of the H8/300 CPU. There are sixteen 8-bit general registers (R0H, R0L, ..., R7H, R7L), which can also be accessed as eight 16-bit registers (R0 to R7). There are two control registers: ...
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General Registers All the general registers can be used as both data registers and address registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as data registers, they can ...
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Bit 7 I Initial value 1 Read/Write R/W R/W * Undetermined Bit 7—Interrupt Mask Bit (I): When this bit is set to "1," all interrupts except NMI are masked. This bit is set to "1" automatically by a reset and ...
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In particular, the stack pointer (R7) is not initialized. To prevent program crashes the stack pointer should be initialized by software, by the first instruction executed after a reset. 1.3 Instructions Features: • The H8/300 has a concise set of ...
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Instruction Functions Tables 1-3 to 1-10 give brief descriptions of the instructions in each functional group. The following notation is used. Notation Rd General register (destination) Rs General register (source) Rn General register (EAd) Destination operand (EAs) Source operand ...
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Table 1-3. Data Transfer Instructions Instruction Size* Function MOV B/W (EAs) register and memory, or moves immediate data to a general register. @Rn+ addressing modes are available for byte or word data. The @aa:8 addressing mode is available for byte ...
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Table 1-4. Arithmetic Instructions Instruction Size* Function ADD B/W Rd ± Rs SUB or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added ...
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Table 1-5. Logic Operation Instructions Instruction Size* Function AND B Rd another general register or immediate data general register or immediate data. XOR B Rd and another general register or immediate data. NOT B ¬ Rd register ...
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Table 1-7. Bit-Manipulation Instructions Instruction Size* Function BSET specified by a bit number, given in 3-bit immediate data or the lower three bits of a general register. BCLR B 0 bit is specified by a bit number, ...
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Table 1-7. Bit-Manipulation Instructions (Cont.) Instruction Size* Function BXOR memory. BIXOR B C general register or memory. BLD B (<bit-No.> of <EAd>) BILD B ¬ (<bit-No.> of <EAd>) memory to the C flag. BST B C BIST ...
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Table 1-8. Branching Instructions Instruction Size Function Bcc — Branches if condition cc is true. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE JMP — Branches unconditionally ...
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Table 1-9. System Control Instructions Instruction Size* Function RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to the power-down state. LDC B Rs Moves immediate data or general register contents to the condition code register. STC ...
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Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are read- modify-write instructions. They read a byte of data, modify one bit in the byte, then write the byte back. Care is required when these instructions are applied ...
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Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since P4DDR is a write-only register read as H'FF, even though its true value is H'3F. Next the CPU clears bit 0 of the read data, ...
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After Execution of BSET Instruction P4 7 Input/output Input Pin state Low DDR Pull-up Off Explanation: To execute the BSET instruction, the CPU begins by reading port 4. Since P4 and P4 6 are input pins, the ...
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P4 7 Input/output Input Pin state Low DDR Pull-up On RAM0 1 Execution of BSET Instruction BSET #0 @RAM0 After Execution of BSET Instruction MOV.B @RAM0 R0L MOV.B R0L @PORT4 ; write value ...
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Machine-Language Coding IMM Notation op: Operation field Register field ...
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Notation op: Operation field Register field IMM: Immediate data Figure 1-6. Machine-Language Coding of Arithmetic, Logic, ...
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Notation op: Operation field ...
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Notation op: Operation field Register field abs.: Absolute address IMM: Immediate data Figure 1-7. Machine-Language Coding of Bit Manipulation Instructions (Cont ...
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Notation op: Operation field cc: Condition field Register field disp.: Displacement abs.: Absolute address and to the I/O port registers. Example 1: ...
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Notation op: Operation field Register field IMM: Immediate data Figure 1-9. Machine-Language Coding of System Control Instructions 15 8 Figure 1-10. Machine-Language Coding of Block Data Transfer Instruction 7 ...
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Addressing Modes and Effective Address Calculation Table 1-11 lists the eight addressing modes and their assembly-language notation. Each instruction can use a specific subset of these addressing modes. Table 1-11. Addressing Modes No. Mode (1) Register direct (2) Register ...
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For a word operand, the original contents of the 16-bit general register must be even. • Register indirect with pre-decrement—@–Rn The @–Rn mode is used with MOV instructions that store registers contents to memory similar to ...
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Calculation of Effective Address: Table 1-12 shows how the H8/300 calculates effective addresses in each addressing mode. Arithmetic, logic, and shift instructions use register direct addressing (1). The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use ...
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Table 1-12, Effective Address Calculation (2) Addressing mode, No. instruction format 3 Register indirect with displacement @(d:16, Rn reg OP disp 4 Register indirect with pre-decrement @- reg OP Register ...
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Table 1-12, Effective Address Calculation (3) Addressing mode, No. instruction format 6 Absolute address @aa abs OP Absolute address @aa: abs 7 PC-relative @(d:8, PC disp OP 8 Memory indirect @@aa:8 15 ...
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Section 2 gives full descriptions of all the H8/300 instructions, presenting them in alphabetic order. Each instruction is explained in a table like the following: ADD (ADD binary) (byte) <Operation> (EAs) Rd <Assembly-Language Format> ADD.B <EAs>, Rd <Examples> ...
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Formats> Name: The full and mnemonic names of the instruction are given at the top of the page. Operation: Describes the instruction in symbolic notation. The following symbols are used. Symbol Meaning (EAs) Source operand (EAd) Destination operand Rs, ...
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The operand size is indicated by the letter B (byte (word). The size is indicated explicitly in this manual, but for instructions that permit only one size, the size designation can be omitted in source-program coding. The abbreviation ...
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Address registers used in the @Rn, @(disp:16, Rn), @Rn+, and @–Rn addressing modes are always 16-bit registers. Data ...
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BLD #5, @H'FF02:8 H'FF02 Loaded to C (carry) flag in CCR The addressing mode and operand size apply to the register or memory byte containing the bit. Number of States Required for Execution: The number of states indicated is the ...
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ADD (ADD binary) (byte) <Operation> (EAs) Rd <Assembly-Language Format> ADD.B <EAs>, Rd <Examples> ADD.B R0H, R1H ADD.B #H'64, R2L <Operand Size> Byte <Description> This instruction adds the source operand to the contents of an 8-bit general register and ...
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ADD (ADD binary) (word) <Operation> <Assembly-Language Format> ADD.W Rs, Rd <Examples> ADD.W R0, R1 <Operand Size> Word <Description> This instruction adds word data in two general registers and places the result in the second general register. ...
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ADDS (ADD with Sign extension) <Operation> <Assembly-Language Format> ADDS #1, Rd ADDS #2, Rd <Examples> ADDS #1, R4 ADDS #2, R5 <Operand Size> Word <Description> This instruction adds the immediate value 1 ...
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ADDX (ADD with eXtend carry) <Operation> (EAs <Assembly-Language Format> ADDX <EAs>, Rd <Examples> ADDX R0L, R1L ADDX #H'0A, R2H <Operand Size> Byte <Description> This instruction adds the source operand and carry flag to the contents ...
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AND (AND logical) <Operation> Rd (EAs) Rd <Assembly-Language Format> AND <EAs>, Rd <Examples> AND R6H, R6L AND #H'FD, R0H <Operand Size> Byte <Description> This instruction ANDs the source operand with the contents of an 8-bit general register and places the ...
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ANDC (AND Control register) <Operation> CCR #IMM CCR <Assembly-Language Format> ANDC #xx:8, CCR <Examples> ANDC #H'7F, CCR <Operand Size> Byte <Description> This instruction ANDs the condition code register (CCR) with immediate data and places the result in the condition code ...
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BAND (Bit AND) <Operation> C (<Bit No.> of <EAd>) <Assembly-Language Format> BAND #xx:3, <EAd> <Examples> BAND #0, R1L BAND #4, @R3 BAND #7, @H'FFE0:8 <Operand Size> Byte <Description> This instruction ANDs a specified bit with the carry flag and places ...
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Bcc (Branch conditionally) <Operation> then PC + d:8 PC else next; <Assembly-Language Format> d:8 Bcc Condition code field (For mnemonics, see the table on the next page.) <Examples> BHI H'42 BEQ H'–7E <Operand Size> — <Condition Code> I ...
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Bcc (Branch conditionally) <Description> If the specified condition is false, this instruction does nothing; the next instruction is executed. If the specified condition is true, a signed displacement is added to the address of the next instruction and execution branches ...
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Bcc (Branch conditionally) <Instruction Formats> Adressing Mnem. mode PC relative BRA (BT) PC relative BRN (BF) PC relative BHI PC relative BLS PC relative BCC (BHS) PC relative BCS (BLO) PC relative BNE PC relative BEQ PC relative BVC PC ...
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BCLR (Bit CLeaR) <Operation> 0 (<Bit No.> of <EAd>) <Assembly-Language Format> BCLR #xx:3, <EAd> BCLR Rn, <EAd> <Examples> BCLR #0, ROL BCLR #1, @R5 BCLR R6L, @H'FFCO:8 <Operand Size> Byte <Description> This instruction clears a specified bit in the destination ...
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BCLR (Bit CLeaR) <Instruction Formats> Addressing Mnem. mode Register direct BCLR Register indirect BCLR Absolute address BCLR Register direct BCLR Register indirect BCLR Absolute address BCLR Instruction code Operands 1st byte 2nd byte #xx: IMM #xx:3,@Rd ...
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BIAND (Bit Invert AND) <Operation> ¬ (<Bit No.> of <EAd>)] <Assembly-Language Format> BIAND #xx:3, <EAd> <Examples> BIAND #0, R1H BIAND #2, @R5 BIAND #4, @H'FFDE:8 <Operand Size> Byte <Description> This instruction ANDs the inverse of a specified bit ...
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BILD (Bit Invert LoaD) <Operation> ¬ (<Bit No.> of <EAd>) <Assembly-Language Format> BILD #xx:3, <EAd> <Examples> BILD #3, R4L BILD #5, @R5 BILD #7, @H'FFA2:8 <Operand Size> Byte <Description> This instruction loads the inverse of a specified bit into the ...
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BIOR (Bit Invert OR) <Operation> C [¬ (<Bit No.> of <EAd>)] <Assembly-Language Format> BIOR #xx:3, <EAd> <Examples> BIOR #6, R1H BIOR #3, @R2 BIOR #0, @H'FFF0:8 <Operand Size> Byte <Description> This instruction ORs the inverse of a specified bit with ...
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BIST (Bit Invert STore) <Operation> ¬ C (<Bit No.> of <EAd>) <Assembly-Language Format> BIST #xx:3, <EAd> <Examples> BIST #0, R0L BIST #6, @R3 BIST #7, @H'FFBB:8 <Operand Size> Byte <Description> This instruction stores the inverse of the carry flag to ...
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BIXOR (Bit Invert eXclusive OR) <Operation> C [¬ (<Bit No.> of <EAd>)] <Assembly-Language Format> BIXOR #xx:3, <EAd> <Examples> BIXOR #1, R4L BIXOR #2, @R5 BIXOR #3, @H'FF60:8 <Operand Size> Byte <Description> This instruction exclusive-ORs the inverse of a specified bitwith ...
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BLD (Bit LoaD) <Operation> (<Bit No.> of <EAd>) <Assembly-Language Format> BLD #xx:3, <EAd> <Examples> BLD #1, R3H BLD #2, @R2 BLD #4, @H'FF90:8 <Operand Size> Byte <Description> This instruction loads a specified bit into the carry flag. The specified bit ...
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BNOT (Bit NOT) <Operation> ¬ (<Bit No.> of <EAd>) (<Bit No.> of <EAd>) <Assembly-Language Format> BNOT #xx:3, <EAd> BNOT Rn, <EAd> <Examples> BNOT #7, R1H BNOT R1L, @R6 BNOT #3, @H'FFB4:8 <Operand Size> Byte <Description> This instruction inverts a specified ...
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BNOT (Bit NOT) <Instruction Formats> Addressing Mnem. mode Register direct BNOT Register indirect BNOT Absolute address BNOT Register direct BNOT Register indirect BNOT Absolute address BNOT Instruction code Operands 1st byte 2nd byte #xx: IMM #xx:3,@Rd ...
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BOR (Bit inclusive OR) <Operation> C (<Bit No.> of <EAd>) <Assembly-Language Format> BOR #xx:3, <EAd> <Examples> BOR #5, R2H BOR #4, @R1 BOR #5, @H'FFB6:8 <Operand Size> Byte <Description> This instruction ORs a specified bit with the carry flag and ...
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BOR (Bit inclusive OR) <Instruction Formats> Addressing Mnem. mode Register direct BOR Register indirect BOR Absolute address BOR Instruction code Operands 1st byte 2nd byte #xx: IMM #xx:3,@ #xx:3,@aa ...
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BSET (Bit SET) <Operation> 1 (<Bit No.> of <EAd>) <Assembly-Language Format> BSET #xx:3,<EAd> BSET Rn,<EAd> <Examples> BSET #3, R2L BSET R2H, @R6 BSET #7, @H'FFE4:8 <Operand Size> Byte <Description> This instruction sets a specified bit in the destination operand to ...
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BSET (Bit SET) <Instruction Formats> Addressing Mnem. mode Register direct BSET Register indirect BSET Absolute address BSET Register direct BSET Register indirect BSET Absolute address BSET Instruction code Operands 1st byte 2nd byte #xx: IMM #xx:3,@Rd ...
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BSR (Branch to SubRoutine) <Operation> PC @– d:8 PC <Assembly-Language Format> BSR d:8 <Examples> BSR H'76 <Operand Size> — <Description> This instruction pushes the program counter (PC) value onto the stack, then adds a specified displacement to the ...
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BST (Bit STore) <Operation> C (<Bit No.> of <EAd>) <Assembly-Language Format> BST #xx:3, <EAd> <Examples> BST #7, R4L BST #2, @R3 BST #6, @H'FFD1:8 <Operand Size> Byte <Description> This instruction stores the carry flag to a specified flag location in ...
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BTST (Bit TeST) <Operation> ¬ (<Bit No.> of <EAd>) <Assembly-Language Format> BTST #xx:3, <EAd> BTST Rn, <EAd> <Examples> BTST #4, R6L BTST R1H, @R5 BTST #7, @H'FF6C:8 <Operand Size> Byte <Description> This instruction tests a specified bit in a general ...
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BTST (Bit TeST) <Instruction Formats> Addressing Mnem. mode Register direct BTST Register indirect BTST Absolute address BTST Register direct BTST Register indirect BTST Absolute address BTST Instruction code Operands 1st byte 2nd byte #xx: IMM #xx:3,@Rd ...
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BXOR (Bit eXclusive OR) <Operation> C (<Bit No.> of <EAd>) <Assembly-Language Format> BXOR #xx:3, <EAd> <Examples> BXOR #4, R6H BXOR #2, @R0 BXOR #1, @H'FFA0:8 <Operand Size> Byte <Description> This instruction exclusive-ORs a specified bit with the carry flag and ...
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BXOR (Bit eXclusive OR) <Instruction Formats> Addressing Mnem. mode Register direct BXOR Register indirect BXOR Absolute address BXOR Instruction code Operands 1st byte 2nd byte #xx: IMM #xx:3,@ #xx:3,@aa ...
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CMP (CoMPare) (byte) <Operation> Rd – (EAs); set condition code <Assembly-Language Format> CMP.B <EAs>, Rd <Examples> CMP.B #H'E5, R1H CMP.B R3L, R4L <Operand Size> Byte <Description> This instruction subtracts an 8-bit source register or immediate data from an 8-bit destination ...
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CMP (CoMPare) (word) <Operation> Rd – Rs; set condition code <Assembly-Language Format> CMP.W Rs, Rd <Examples> CMP.W R5, R6 <Operand Size> Word <Description> This instruction subtracts a source register from a destination register and sets the condition code flags according ...
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DAA (Decimal Adjust Add) <Operation> Rd (decimal adjust) Rd <Assembly-Language Format> DAA Rd <Examples> DAA R5L <Operand Size> Byte <Description> Given that the result of an addition operation performed by the ADD.B or ADDX instruction on 4-bit BCD data is ...
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DAA (Decimal Adjust Add) <Instruction Formats> Addressing Mnem. mode Register direct DAA Instruction code Operands 1st byte 2nd byte DAA 3rd byte 4th byte rd No. of states 2 ...
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DAS (Decimal Adjust Subtract) <Operation> Rd (decimal adjust) Rd <Assembly-Language Format> DAS Rd <Examples> DAS R0H <Operand Size> Byte <Description> Given that the result of a subtraction operation performed by the SUB.B, SUBX, or NEG instruction on 4-bit BCD data ...
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DAS (Decimal Adjust Subtract) <Instruction Formats> Addressing Mnem. mode Register direct DAS Instruction code Operands 1st byte 2nd byte 3rd byte 4th byte rd DAS No. of states 2 ...
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DEC (DECrement) <Operation> Rd – <Assembly-Language Format> DEC Rd <Examples> DEC R2L <Operand Size> Byte <Description> This instruction decrements an 8-bit general register and places the result in the 8-bit general register. <Instruction Formats> Addressing Mnem. mode Register ...
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DIVXU (DIVide eXtend as Unsigned) <Operation> Rd ÷ <Assembly-Language Format> DIVXU Rs, Rd <Examples> DIVXU R0L, R1 <Operand Size> Byte <Description> This instruction divides a 16-bit general register by an 8-bit general register and places the result in ...
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DIVXU (DIVide eXtend as Unsigned) <Note: DIVXU Overflow> Since the DIVXU instruction performs 16-bit ÷ 8-bit if the divisor byte is equal to or less than the upper byte of the dividend. For example, H'FFFF ÷ H'01 H'FFFF causes an ...
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EEPMOV (MOVe data to EEPROM) <Operation> if R4L ≠ 0 then repeat @R5+ R4L – 1 until R4L = 0 else next; <Assembly-Language Format> EEPMOV <Examples> MOV.B #H'20, R4L MOV.W #H'FEC0, R5 MOV.W #H'6000, R6 EEPMOV <Operand Size> — <Description> ...
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EEPMOV (MOV data to EEPROM) <Instruction Formats> Addressing Mnem. mode EEPMOV * n is the initial value in R4L (0 ≤ n ≤ 255). Although n bytes of data are transferred, memory is accessed 2(n+1) times, requiring 4(n+1) states. Notes ...
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INC (INCrement) <Operation> <Assembly-Language Format> INC Rd <Examples> INC R3L <Operand Size> Byte <Description> This instruction increments an 8-bit general register and places the result in the 8-bit general register. <Instruction Formats> Addressing Mnem. mode Register ...
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JMP (JuMP) <Operation> (EAd) PC <Assembly-Language Format> JMP <EA> <Examples> JMP @R6 JMP @H'2000 JMP @@H'9A <Operand Size> — <Description> This instruction branches unconditionally to a specified destination address. The destination address must be even. <Instruction Formats> Addressing Mnem. mode ...
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JSR (Jump to SubRoutine) <Operation> PC @-SP (EAd) PC <Assembly-Language Format> JSR <EA> <Examples> JSR @R3 JSR @H'1D26 JSR @@H'F0 <Operand Size> <Description> This instruction pushes the program counter onto the stack, then branches to a specified destination address. The ...
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LDC (LoaD to Control register) <Operation> (EAs) CCR <Assembly-Language Format> LDC <EAs>, CCR <Examples> LDC #H'80, CCR LDC R4H, CCR <Operand Size> Byte <Description> This instruction loads the source operand contents into the condition code register (CCR). The source operand ...
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MOV (MOVe data) (byte) <Operation> <Assembly-Language Format> MOV.B Rs, Rd <Examples> MOV.B R1L, R2H <Operand Size> Byte <Description> This instruction moves one byte of data from a source register to a destination register and sets condition code flags ...
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MOV (MOVe data) (word) <Operation> <Assembly-Language Format> MOV.W Rs, Rd <Examples> MOV.W R3, R4 <Operand Size> Word <Description> This instruction moves one word of data from a source register to a destination register and sets condition code flags ...
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MOV (MOVe data) (byte) <Operation> (EAs) Rd <Assembly-Language Format> MOV.B <EAs>, Rd <Examples> MOV.B @R1, R2H MOV.B @R5+, R0L MOV.B @H'FFF1, R1H MOV.B #H'A5, R3L <Operand Size> Byte <Description> This instruction moves one byte of data from a source operand ...
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MOV (MOVe data) (word) <Operation> (EAs) Rd <Assembly-Language Format> MOV.W <EAs>, Rd <Examples> MOV.W @R3, R4 MOV.W @(H'0004,R5), R6 MOV.W @R7+, R0 MOV.W #H'B00A, R1 <Operand Size> Word <Description> This instruction moves one word of data from a source operand ...
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MOV (MOVe data) (byte) <Operation> Rs (EAd) <Assembly-Language Format> MOV.B Rs, <EAd> <Examples> MOV.B R1L, @R0 MOV.B R3H, @(H'8001, R0) MOV.B R5H, @–R4 MOV.B R6L, @H'FE77 <Operand Size> Byte <Description> This instruction moves one byte of data from a source ...
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MOV (MOVe data) (word) <Operation> Rs (EAd) <Assembly-Language Format> MOV.W Rs, <EAd> <Examples> MOV.W R3, @R4 MOV.W R2, @(H,0030,R5) MOV.W R1, @–R7 MOV.W R0, @H'FED6 <Operand Size> Word <Description> This instruction moves one word of data from a general register ...
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MOVFPE (MOVe data From Peripheral with E clock) <Operation> synchronization with the E clock (EAs) Rd <Assembly-Language Format> MOVFPE @aa:16, Rd <Examples> MOVFPE @H'FF81, R0H <Operand Size> Byte <Description> This instruction moves one byte of data from an absolute address ...
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MOVTPE (MOVe data To Peripheral with E clock) <Operation> synchronization with the E clock Rs (EAd) <Assembly-Language Format> MOVTPE Rs, @aa:16 <Examples> MOVTPE R2L, @H'FF8D <Operand Size> Byte <Description> This instruction moves one byte of data from a source register ...
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MULXU (MULtiply eXtend as Unsigned) <Operation> <Assembly-Language Format> MULXU Rs, Rd <Examples> MULXU R0H, R3 <Operand Size> Byte <Description> This instruction performs 8-bit 8-bit register by a source register and places the result in the destination register. ...
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NEG (NEGate) <Operation> 0 – <Assembly-Language Format> NEG Rd <Examples> NEG R0L <Operand Size> Byte <Description> This instruction replaces the contents of an 8-bit general register with its two's complement. (subtracts the register contents from H'00). If the ...
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NOP (No OPeration) <Operation> <Assembly-Language Format> NOP <Examples> NOP <Operand Size> ___ <Description> This instruction only increments the program counter, causing the next instruction to be executed. The internal state of the CPU does not change. ...
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NOT (NOT = logical complement) <Operation> ¬ <Assembly-Language Format> NOT Rd <Examples> NOT R4L <Operand Size> Byte <Description> This instruction replaces the contents of an 8-bit general register with its one's complement (subtracts the register contents from H'FF). ...
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OR (inclusive OR logical) <Operation> Rd (EAs) Rd <Assembly-Language Format> OR <EAs>, Rd <Examples> OR R2H, R3H OR #H'C0, R0H <Operand Size> Byte <Description> This instruction ORs the source operand with the contents of an 8-bit general register and places ...
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ORC (inclusive OR Control register) <Operation> CCR #IMM CCR <Assembly-Language Format> ORC #xx:8, CCR <Examples> ORC #H'80, CCR <Operand Size> Byte <Description> This instruction ORs the condition code register (CCR) with immediate data and places the result in the condition ...
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POP (POP data) <Operation> @SP+ Rn <Assembly-Language Format> POP Rn <Examples> POP R1 <Operand Size> Word <Description> This instruction pops data from the stack to a 16-bit general register and sets condition code flags according to the data value. POP.W ...
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PUSH (PUSH data) <Operation> Rn @–SP <Assembly-Language Format> PUSH Rn <Examples> PUSH R2 <Operand Size> Word <Description> This instruction pushes data from a 16-bit general register onto the stack and sets condition code flags according to the data value. PUSH.W ...
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ROTL (ROTate Left) <Operation> Rd (rotated left) Rd <Assembly-Language Format> ROTL Rd <Examples> ROTL R2L <Operand Size> Byte <Description> This instruction rotates an 8-bit general register one bit to the left. The most significant bit is rotated to the least ...
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ROTR (ROTate Right) <Operation> Rd (rotated right) Rd <Assembly-Language Format> ROTR Rd <Examples> ROTR R5L <Operand Size> Byte <Description> This instruction rotates an 8-bit general register one bit to the right. The least significant bit is rotated to the most ...
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ROTXL (ROTate with eXtend carry Left) <Operation> Rd (rotated with carry left) <Assembly-Language Format> ROTXL Rd <Examples> ROTXL R1H <Operand Size> Byte <Description> This instruction rotates an 8-bit general register one bit to the left through the carry flag. The ...
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ROTXR (ROTate with eXtend carry Right) <Operation> Rd (rotated with carry right) <Assembly-Language Format> ROTXR Rd <Examples> ROTXR R5L <Operand Size> Byte <Description> This instruction rotates an 8-bit general register one bit to the right through the carry flag. The ...
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RTE (ReTurn from Exception) <Operation> @SP+ CCR @SP+ PC <Assembly-Language Format> RTE <Examples> RTE <Operand Size> — <Description> This instruction returns from an interrupt-handling routine. It pops the condition code register (CCR) and program counter (PC) from the stack. Program ...
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RTS (ReTurn from Subroutine) <Operation> @SP+ PC <Assembly-Language Format> RTS <Examples> RTS <Operand Size> — <Description> This instruction returns from a subroutine. It pops the program counter (PC) from the stack. Program execution continues from the address restored to the ...
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SHAL (SHift Arithmetic Left) <Operation> Rd (shifted arithmetic left ) <Assembly-Language Format> SHAL Rd <Examples> SHAL R5H <Operand Size> Byte <Description> This instruction shifts an 8-bit general register one bit to the left. The most significant bit shifts into the ...
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SHAR (SHift Arithmetic Right) <Operation> Rd (shifted arithmetic right ) <Assembly-Language Format> SHAR Rd <Examples> SHAR R5H <Operand Size> Byte <Description> This instruction shifts an 8-bit general register one bit to the right. The most significant bit remains unchanged. The ...
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SHLL (SHift Logical Left) <Operation> Rd (shifted logical left ) <Assembly-Language Format> SHLL Rd <Examples> SHLL R2L <Operand Size> Byte <Description> This instruction shifts an 8-bit general register one bit to the left. The least significant bit is cleared to ...
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SHLR (SHift Logical Right) <Operation> Rd (shifted logical right ) <Assembly-Language Format> SHLR Rd <Examples> SHLR R3L <Operand Size> Byte <Description> This instruction shifts an 8-bit general register one bit to the right. The most significant bit is cleared to ...
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SLEEP (SLEEP) <Operation> Program execution state down mode <Assembly-Language Format> SLEEP <Examples> SLEEP <Operand Size> — <Description> When the SLEEP instruction is executed, the CPU enters a power-down mode. Its internal state remains unchanged, but the CPU stops executing instructions ...
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STC (STore from Control register) <Operation> CCR Rd <Assembly-Language Format> STC CCR, Rd <Examples> STC CCR, R6H <Operand Size> Byte <Description> This instruction copies the condition code register (CCR specified general register. Bits 6 and 4 are copied ...
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SUB (SUBtract binary) (byte) <Operation> Rd – <Assembly-Language Format> SUB.B Rs, Rd <Examples> SUB.B R0L, R2L <Operand Size> Byte <Description> This instruction subtracts an 8-bit source register from an 8-bit destination register and places the result in the ...
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SUB (SUBtract binary) (byte) <Instruction Formats> Addressing Mnem. mode Register direct SUB.B Operands 1st byte 2nd byte Rs 111 Instruction code 3rd byte 4th byte rd SUB No. of states 2 ...
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SUB (SUBtract binary) (word) <Operation> <Assembly-Language Format> SUB.W Rs, Rd <Examples> SUB.W R0, R1 <Operand Size> Word <Description> This instruction subtracts a 16-bit source register from a 16-bit destination register and places the result in the ...
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SUBS (SUBtract with Sign extension) <Operation> Rd – – <Assembly-Language Format> SUBS #1, Rd SUBS #2, Rd <Examples> SUBS #1, R3 SUBS #2, R5 <Operand Size> Word <Description> This instruction subtracts the immediate value 1 ...
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SUBX (SUBtract with eXtend carry) <Operation> Rd – (EAs) – <Assembly-Language Format> SUBX <EAs>, Rd <Examples> SUBX R0L, R3L SUBX #H'32, R5H <Operand Size> Byte <Description> This instruction subtracts the source operand and carry flag from the contents ...
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XOR (eXclusive OR logical) <Operation> Rd (EAs) Rd <Assembly-Language Format> XOR <EAs>, Rd <Examples> XOR R0H, R1H XOR #H'F0, R2L <Operand Size> Byte <Description> This instruction exclusive-ORs the source operand with the contents of an 8-bit general register and places ...
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XORC (eXclusive OR Control register) <Operation> CCR #IMM CCR <Assembly-Language Format> XORC #xx:8, CCR <Examples> XORC #H'50, CCR <Operand Size> Byte <Description> This instruction exclusive-ORs the condition code register (CCR) with immediate data and places the result in the condition ...
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117 ...
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Appendix. B Instruction Set List Mnemonic B MOV.B #xx:8,Rd #xx:8 B Rs8 MOV.B Rs,Rd B MOV.B @Rs,Rd @Rs16 B @(d:16,Rs16) MOV.B @(d:16,Rs),Rd @Rs16 B MOV.B @Rs+,Rd Rs16+1 @aa:8 MOV.B @aa:8, @aa:16 MOV.B @aa:16,Rd B Rs8 MOV.B Rs,@Rd Rs8 ...
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Mnemonic ADD.B #xx:8,Rd B Rd8+#xx:8 ADD.B Rs,Rd B Rs8+Rd8 Rs16+Rd16 ADD.W Rs,Rd W Rd8+#xx:8+C ADDX.B #xx:8, Rd8+Rs8+C ADDX.B Rs,Rd Rd16+1 ADDS.W #1, Rd16+2 ADDS.W #2,Rd B Rd8+1 INC DAA.B Rd Rd8 decimal adjust B ...
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Mnemonic C SHAL SHAR SHLL SHLR ROTXL ROTXR ROTL ROTR (#xx:3 of Rd8) B BSET #xx:3,Rd (#xx:3 of @Rd16) BSET ...
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Mnemonic B (Rn8 of Rd8) BNOT Rn,Rd (Rn8 of @Rd16) (Rn8 of @Rd16) B BNOT Rn,@Rd (Rn8 of @aa:8) (Rn8 of @aa:8) B BNOT Rn,@aa:8 (#xx:3 of Rd8) BTST #xx:3, (#xx:3 of @Rd16) BTST #xx:3,@Rd B (#xx:3 of ...
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Mnemonic B C (#xx:3 of @Rd16) BIOR #xx:3,@Rd C (#xx:3 of @aa:8) B BIOR #xx:3,@aa:8 BXOR #xx:3, (#xx:3 of Rd8) BXOR #xx:3,@ (#xx:3 of @Rd16) B BXOR #xx:3,@aa:8 C (#xx:3 of @aa:8) BIXOR #xx:3, ...
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Mnemonic – SP–2 JSR @aa: – JSR @@aa:8 SP– – RTS PC SP+2 – CCR RTE SP+2 PC SP+2 – Transit to sleep mode. SLEEP LDC #xx:8,CCR B #xx:8 LDC Rs,CCR Rs8 B CCR STC CCR,Rd ...
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Appendix C. Number of Execution States The tables in this appendix can be used to calculate the number of states required for instruction execution. Table C-1 indicates the number of states required for each cycle (instruction fetch, branch address read, ...
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Table C-1. Number of States Taken by Each Cycle in Instruction Execution Execution Status (instruction cycle) Instruction fetch S I Branch address read S J Stack operation S K Byte data access S L Word data access S M Internal ...
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Table C-2. Number of Cycles in Each Instruction Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDS.W #1/2, Rd ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd AND AND.B #xx:8, Rd AND.B Rs, Rd ANDC ANDC ...
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Instruction Mnemonic BCLR BCLR Rn, @Rd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BILD BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 BIST ...
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Instruction Mnemonic BSET BSET Rn, @aa:8 BSR BSR d:8 BST BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BTST BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 BXOR BXOR ...
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Instruction Mnemonic MOV MOV.B @(d:16, Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @–Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, ...
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Instruction Mnemonic SHAL SHAL.B Rd SHAR SHAR.B Rd SHLL SHLL.B Rd SHLR SHLR.B Rd SLEEP SLEEP STC STC CCR, Rd SUB SUB.B Rs, Rd SUB.W Rs, Rd SUBS SUBS.W #1/2, Rd SUBX SUBX.B #xx:8, Rd SUBX.B Rs, Rd XOR XOR.B ...
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H8/300 Programming Manual Publication Date: 1st Edition, December 1989 Published by: Business Planning Division Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright © Hitachi, Ltd., 1989. All rights reserved. Printed in ...