HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 27

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are read-
modify-write instructions. They read a byte of data, modify one bit in the byte, then write the
byte back. Care is required when these instructions are applied to registers with write-only bits
and to the I/O port registers.
Sequence
1 Read
2 Modify
3 Write
Example 1: BCLR is executed to clear bit 0 in the port 4 data direction register (P4DDR)
under the following conditions.
P4
P4
P4
The intended purpose of this BCLR instruction is to switch P4
Before Execution of BCLR Instruction
Input/output
Pin state
DDR
DR
Pull-up
Execution of BCLR Instruction
BCLR
After Execution of BCLR Instruction
Input/output
Pin state
DDR
DR
Pull-up
7
6
5
:
:
– P4
0
#0
:
Input pin, Low, MOS pull-up transistor on
Input pin, High, MOS pull-up transistor off
Output pins, Low
@P4DDR
Operation
Read one data byte at the specified address
Modify one bit in the data byte
Write the modified data byte back to the specified address
P4
Input
Low
0
1
On
P4
Output Output Output Output Output Output Output Input
Low
1
1
Off
7
7
P4
Input
High
0
0
Off
P4
High
1
0
Off
6
6
; clear bit 0 in data direction register
P4
Output Output Output Output Output Output
Low
1
0
Off
P4
Low
1
0
Off
5
5
P4
Low
1
0
Off
P4
Low
1
0
Off
17
4
4
P4
Low
1
0
Off
P4
Low
1
0
Off
3
3
P4
Low
1
0
Off
P4
Low
1
0
Off
0
from output to input.
2
2
P4
Low
1
0
Off
P4
Low
1
0
Off
1
1
P4
Low
1
0
Off
P4
High
0
0
Off
0
0