HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 84

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

DIVXU (DIVide eXtend as Unsigned)
<Description>
This instruction divides a 16-bit general register by an 8-bit general register and places the
result in the 16-bit general register. The quotient is placed in the lower byte. The remainder is
placed in the upper byte. The operation is shown schematically below.
Valid results are not assured if division by zero is attempted or an overflow occurs. Division
by zero is indicated in the Zero flag. Overflow can be avoided by the coding shown on the
next page.
<Instruction Formats>
<Operation>
Rd ÷ Rs
<Assembly-Language Format>
DIVXU Rs, Rd
<Examples>
DIVXU R0L, R1
<Operand Size>
Byte
Register direct
Addressing
mode
Dividend
Rd
Rd
16
Mnem.
DIVXU
÷
Operands
Rs, Rd
Divisor
Rs
8
1st byte
5
74
1
Instruction code
<Condition Code>
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to "1" if the divisor is negative;
Z: Set to "1" if the divisor is zero;
V: Previous value remains unchanged.
C: Previous value remains unchanged.
Remainder Quotient
otherwise cleared to "0."
otherwise cleared to "0."
2nd byte
— — — —
rs
I
(RdH)
8
0 rd
Rd
H
3rd byte
(RdL)
8
N
4th byte
Z
— —
DIVXU
V
No. of
states
C
14