HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 14

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Memory Data Structure: Figure 1-2 indicates the data structure in memory.
Word data stored in memory must always begin at an even address. In word access the least
significant bit of the address is regarded as “0.” If an odd address is specified, no address error
occurs but the access is performed at the preceding even address. This rule affects MOV.W
instructions and branching instructions, and implies that only even addresses should be stored
in the vector table.
The stack is always accessed a word at a time. When the CCR is pushed on the stack, two
identical copies of the CCR are pushed to make a complete word. When they are returned, the
lower byte is ignored.
1.1.3 Address Space
The H8/300 CPU supports a 64K-byte address space. The memory map differs depending on
the particular chip in the H8/300 Series and its operating mode. See the Hardware Manual of
the chip for details.
CCR: Condition code register.
Note: Word data must begin at an even address.
*
:
Ignored when return.
1-Bit data
Byte data
Word data
Byte data (CCR) on stack
Word data on stack
Data type
Figure 1-2. Memory Data Formats
Address
Address n
Address n
Even address
Even address
Even address
Odd address
Odd address
Odd address
4
7 6 5 4 3 2 1 0
7
M
S
B
M
S
B
M
S
B
M
S
B
M
S
B
Data format
Upper 8 bits
Upper 8 bits
Lower 8 bits
Lower 8 bits
CCR
CCR
*
0
L
S
B
L
S
B
L
S
B
L
S
B
L
S
B