HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 38

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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(5) Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of
the operand in memory. The @aa:8 mode uses an 8-bit absolute address of the form H’FFxx.
The upper 8 bits are assumed to be 1, so the possible address range is H’FF00 to H’FFFF
(65280 to 65535). The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute
addresses.
(6) Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand in its second
byte, or a 16-bit operand in its third and fourth bytes. Only MOV.W instructions can contain
16-bit immediate values.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data.
Some bit manipulation instructions contain 3-bit immediate data (#xx:3) in the second or
fourth byte of the instruction, specifying a bit number.
(7) PC-Relative—@(d:8, PC): This mode is used to generate branch addresses in the Bcc
and BSR instructions. An 8-bit value in byte 2 of the instruction code is added as a sign-
extended value to the program counter contents. The result must be an even number. The
possible branching range is –126 to +128 bytes (–63 to +64 words) from the current address.
(8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions.
The second byte of the instruction code specifies an 8-bit absolute address from H’0000 to
H’00FF (0 to 255). Note that the initial part of the area from H'0000 to H'00FF contains the
exception vector table. See the hardware manual of the specific chip for details. The word
located at this address contains the branch address.
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as “0,” causing word access to be performed at
the address preceding the specified address. See the memory data structure description in
section 1.1.2, Data Structure.
word operand. For a word operand, the original contents of the 16-bit general register
must be even.
Register indirect with pre-decrement—@–Rn
The @–Rn mode is used with MOV instructions that store registers contents to memory.
It is similar to the register indirect mode, but the 16-bit general register specified in the
register field of the instruction is decremented before the operand is accessed. The size of
the decrement is 1 or 2 depending on the size of the operand: 1 for a byte operand; 2 for a
word operand. For a word operand, the original contents of the 16-bit general register
must be even.
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