HD64F3337YCP16 Renesas Electronics America, HD64F3337YCP16 Datasheet - Page 12

• Manufacturer Part Number: HD64F3337YCP16
• Description: IC H8 MCU FLASH 60K 84PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300r

Specifications of HD64F3337YCP16

• Core Processor: H8/300
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: Host Interface, I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 84-PLCC
• Package: 84PLCC
• Family Name: H8
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 74
• Interface Type: HIF/I2C/SCI
• On-chip Adc: 8-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Item
Address space
Data types
General registers
Control registers
Addressing modes
Instruction length
1.1 General CPU Architecture
1.1.1 Features
Table 1-1 summarizes the CPU architecture. Figures 1-1 and 1-2 show how data are
stored in registers and memory.
Table 1-1. CPU Architecture
Notes:
1. Word data stored in memory must be stored at an even address.
2. Instructions must be stored at even addresses.
3. General register R7 is used as the stack pointer (SP).
1.1.2 Data Structure
The H8/300 CPU can process 1-bit data, 4-bit (packed BCD) data, 8-bit (byte) data, and 16-bit
(word) data.
•
•
Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a
All operational instructions except ADDS and SUBS can operate on byte data.
byte operand.
Description
64K bytes, H'0000 to H'FFFF
Bit, 4-bit (packed BCD), byte, word (2 bytes)
Sixteen 8-bit general registers (R0H, R0L, ..., R7H, R7L),
also accessible as eight 16-bit general registers (R0 to R7)
Program counter (PC)
Condition code register (CCR)
Rn
@Rn
@(d:16, Rn)
@Rn+
@–Rn
@aa:8, @aa:16
#xx:8, #xx:16
@(d:8, PC)
@@aa:8
2 or 4 bytes
2
Register direct
Register indirect
Register indirect with 16-bit displacement
Register indirect with post-increment
Register indirect with pre-decrement
Absolute address (8 or 16 bits)
Immediate (8-, or 16-bit data)
PC-relative (8-bit displacement)
Memory indirect