HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 216

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

OCRF is a 16-bit read/write output compare register consisting of two 8-bit read/write registers
OCRFH and OCRFL. It can be used as a 16-bit output compare register, with OCRFH as the
upper 8 bits and OCRFL as the lower 8 bits of the register, or OCRFH and OCRFL can be used as
independent 8-bit registers.
OCRFH and OCRFL can be read and written by the CPU, but in 16-bit mode, data transfer with
the CPU takes place via a temporary register (TEMP). For details see 9.5.3, Interface with the
CPU.
Upon reset, OCRFH and OCRFL are each initialized to H'FF.
Timer Control Register F (TCRF)
TCRF is an 8-bit write-only register. It is used to switch between 16-bit mode and 8-bit mode, to
select among four internal clocks and an external clock, and to select the output level at pins
TMOFH and TMOFL.
Upon reset, TCRF is initialized to H'00.
Bit
Initial value
Read/Write
16-bit mode (OCRF)
16-bit mode is selected by clearing bit CKSH2 to 0 in timer control register F (TCRF). The
OCRF contents are always compared with the 16-bit timer counter (TCF). When the contents
match, the compare match flag (CMFH) in TCSRF is set to 1. Also, IRRTFH in interrupt
request register 2 (IRR2) is set to 1. If bit IENTFH in interrupt enable register 2 (IENR2) is set
to 1, a CPU interrupt is requested.
Output for pin TMOFH can be toggled by compare match. The output level can also be set to
high or low by bit TOLH of timer control register F (TCRF).
8-bit mode (OCRFH, OCRFL)
Setting bit CKSH2 in TCRF to 1 results in two 8-bit registers, OCRFH and OCRFL.
The OCRFH contents are always compared with TCFH, and the OCRFL contents are always
compared with TCFL. When the contents match, the compare match flag (CMFH or CMFL) in
TCSRF is set to 1. Also, bit IRRTFH (IRRTFL) in interrupt request register 2 (IRR2) set to 1.
If bit IENTFH (IENTFL) in interrupt enable register 2 (IENR2) is set to 1 at this time, a CPU
interrupt is requested.
The output at pin TMOFH (TMOFL) can be toggled by compare match. The output level can
also be set to high or low by bit TOLH (TOLL) of the timer control register (TCRF).
TOLH
W
7
0
CKSH2
W
6
0
CKSH1
W
5
0
CKSH0
W
4
0
TOLL
W
3
0
CKSL2
W
2
0
CKSL1
W
1
0
CKSL0
W
0
0
199