HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 269

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Transmit Data Register (TDR)
The transmit data register (TDR) is an 8-bit register for holding transmit data.
When SCI3 detects that the transmit shift register (TSR) is empty, it shifts transmit data written in
TDR to TSR and starts serial data transmission. While TSR is transmitting serial data, the next
byte to be transmitted can be written to TDR, realizing continuous transmission.
TDR can be read or written by the CPU at all times.
TDR is initialized to H'FF upon reset or in standby mode, watch mode, subactive mode, or
subsleep mode.
Serial Mode Register (SMR)
The serial mode register (SMR) is an 8-bit register for setting the serial data communication
format and for selecting the clock source of the baud rate generator. SMR can be read and written
by the CPU at any time.
SMR is initialized to H'00 upon reset or in standby mode, watch mode, subactive mode, or
subsleep mode.
Bit 7—Communication Mode (COM): Bit 7 selects asynchronous mode or synchronous mode as
the serial data communication mode.
Bit 7: COM
0
1
252
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
TDR7
COM
R/W
R/W
Description
Asynchronous mode
Synchronous mode
7
1
7
0
TDR6
CHR
R/W
R/W
6
1
6
0
TDR5
R/W
R/W
PE
5
1
5
0
TDR4
R/W
R/W
PM
4
1
4
0
STOP
TDR3
R/W
R/W
3
1
3
0
TDR2
R/W
R/W
MP
2
1
2
0
CKS1
TDR1
R/W
R/W
1
1
1
0
(initial value)
CKS0
TDR0
R/W
R/W
0
1
0
0