HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 298

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

SCI3 operates as follows during data transmission in synchronous mode.
SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data
written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR).
Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is
requested.
If clock output is selected, SCI3 outputs eight serial clock pulses. If an external clock is used, data
is output in synchronization with the clock input.
Serial data is transmitted from pin TXD in order from LSB (bit 0) to MSB (bit 7).
Then TDRE is checked as the MSB (bit 7) is being transmitted. If TDRE is 0, data is transferred
from TDR to TSR, and after the MSB (bit 7) is sent, transmission of the next frame starts. If
TDRE is 1, the TEND bit in SSR is set to 1, and after the MSB (bit 7) has been sent, the MSB
state is maintained. A TEI interrupt is requested in this state if bit TEIE in SCR3 is set to 1.
After data transmission ends, pin SCK
Note: Data transmission cannot take place while any of the receive error flags (OER, FER, PER)
Figure 10.18 shows a typical SCI3 transmit operation in synchronous mode.
Serial
clock
Serial data
TDRE
TEND
SCI3
operation
User
processing
is set to 1. Be sure to confirm that these error flags are cleared to 0 before starting
transmission.
Figure 10.18 Typical SCI3 Transmit Operation in Synchronous Mode
TXI
request
Bit 0
TDRE cleared to 0
Write data in TDR
Bit 1
1 frame
3
is held at the high level.
TXI
request
Bit 7
Bit 0
Bit 1
1 frame
Bit 6
TEI request
Bit 7
281