HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 39

MCU 5V 32K PB-FREE 100-QFP

HD6473834HV

Manufacturer Part Number
HD6473834HV
Description
MCU 5V 32K PB-FREE 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet

Specifications of HD6473834HV

Core Processor
H8/300L
Core Size
8-Bit
Speed
5MHz
Connectivity
SCI
Peripherals
LCD, PWM
Number Of I /o
71
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Manufacturer
Quantity
Price
Part Number:
HD6473834HV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6473834HV
Manufacturer:
RENESAS
Quantity:
2 120
8. Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
second byte of the instruction code specifies an 8-bit absolute address. The word located at this
address contains the branch destination address.
The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from
H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the address area
is also used as a vector area. See 3.3, Interrupts, for details on the vector area.
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as 0, causing word access to be performed at the
address preceding the specified address. See 2.3.2, Memory Data Formats, for further information.
2.4.2
Effective Address Calculation
Table 2.2 shows how effective addresses are calculated in each of the addressing modes.
Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX,
CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6).
Data transfer instructions can use all addressing modes except program-counter relative (7) and
memory indirect (8).
Bit manipulation instructions use register direct (1), register indirect (2), or absolute addressing (8-
bit) (5) to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit position in
that byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing
(1) to specify the bit position.
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