HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 305

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

SCI3 operates as follows during data transmission using a multiprocessor format.
SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data
written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR).
Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is
requested.
Serial data is transmitted from pin TXD using the communication format outlined in
table 10.16.
Next, TDRE is checked as the stop bit is being transmitted. If TDRE is 0, data is transferred from
TDR to TSR, and after the stop bit is sent, transmission of the next frame starts. If TDRE is 1, the
TEND bit in SSR is set to 1, and after the stop bit is sent the output remains at 1 (mark state). A
TEI interrupt is requested in this state if bit TEIE in SCR3 is set to 1.
Figure 10.24 shows a typical SCI3 operation in multiprocessor communication mode.
288
Serial
data
TDRE
TEND
SCI3
operation
User
processing
1
TXI request
Start
bit
Figure 10.24 Typical Multiprocessor Format Transmit Operation
0
(8-Bit Data, Multiprocessor Bit Added, and 1 Stop Bit)
D0
TDRE cleared
to 0
Write data in
TDR
D1
Transmit
data
1 frame
D7
MPB
0/1
TXI
request
Stop
bit
1
Start
bit
0
D0
D1
Transmit
data
1 frame
D7
MPB
0/1
TEI
request
Stop
bit
1
Mark
state
1