HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 248

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Serial Data Register L (SDRL)
SDRL is an 8-bit read/write register. It is used as the data register in 8-bit transfer, and as the data
register for the lower 8 bits in 16-bit transfer (SDRU is used for the upper 8 bits).
In 8-bit transfer, data written to SDRL is output from pin SO
(LSB). This data is than replaced by LSB-first data input at pin SI
direction from the most significant bit (MSB) toward the LSB.
In 16-bit transfer, operation is the same as for 8-bit transfer, except that input data is fed in via
SDRU.
SDRL must be written or read only after data transmission or reception is complete. If this register
is read or written while a data transfer is in progress, the data contents are not guaranteed.
The SDRL value upon reset is not fixed.
10.2.3
Data can be sent and received in an 8-bit or 16-bit format, synchronized to an internal or external
serial clock. Overrun errors can be detected when an external clock is used.
Clock
The serial clock can be selected from a choice of eight internal clocks and an external clock. When
an internal clock source is selected, pin SCK
clock output mode is selected (SCR1 bits SNC1 and SNC0 are set to 10), the clock signal ( /1024
to /2) selected in bits CKS2 to CKS0 is output continuously from pin SCK
clock is used, pin SCK
Data Transfer Format
Figure 10.2 shows the data transfer format. Data is sent and received starting from the least
significant bit, in LSB-first format. Transmit data is output from one falling edge of the serial
clock until the next falling edge. Receive data is latched at the rising edge of the serial clock.
Bit
Initial value
Read/Write
Operation
Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed Not fixed
SDRL7
R/W
7
1
is the clock input pin.
SDRL6
R/W
6
SDRL5
R/W
5
1
becomes the clock output pin. When continuous
SDRL4
R/W
4
SDRL3
1
R/W
starting from the least significant bit
3
1
, which is shifted in the
SDRL2
R/W
2
1
. When an external
SDRL1
R/W
1
SDRL0
R/W
0
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