HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 324

MCU 5V 32K PB-FREE 100-QFP

HD6473834HV

Manufacturer Part Number
HD6473834HV
Description
MCU 5V 32K PB-FREE 100-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet

Specifications of HD6473834HV

Core Processor
H8/300L
Core Size
8-Bit
Speed
5MHz
Connectivity
SCI
Peripherals
LCD, PWM
Number Of I /o
71
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6473834HV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6473834HV
Manufacturer:
RENESAS
Quantity:
2 120
12.4
When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request
register 2 (IRR2) is set to 1.
A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt
enable register 2 (IENR2).
For further details see 3.3, Interrupts.
12.5
An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as
the analog input channel. Figure 12.3 shows the operation timing.
If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place.
Figures 12.4 and 12.5 show flow charts of procedures for using the A/D converter.
Bits CH3 to CH0 of the A/D mode register (AMR) are set to 0101, making pin AN
input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is
started by setting bit ADSF to 1.
When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion result is
stored in the A/D result register (ADRR). At the same time ADSF is cleared to 0, and the A/D
converter goes to the idle state.
Bit IENAD = 1, so an A/D conversion end interrupt is requested.
The A/D interrupt handling routine starts.
The A/D conversion result is read and processed.
The A/D interrupt handling routine ends.
Pin ADTRG
(when bit
IEG4 = 0)
ADSF
Interrupts
Typical Use
Figure 12.2 External Trigger Input Timing
A/D conversion
1
the analog
307

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