HD6473834HV Renesas Electronics America, HD6473834HV Datasheet - Page 233

• Manufacturer Part Number: HD6473834HV
• Description: MCU 5V 32K PB-FREE 100-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473834HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 71
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The noise canceller consists of five latch circuits connected in series, and a match detection
circuit. When the noise canceller function is disabled (NCS = 0), the system clock is selected as
the sampling clock. When the noise canceller is enabled (NCS = 1), the internal clock selected by
bits CKS1 and CKS0 in TMG becomes the sampling clock. The input signal is sampled at the
rising edge of this clock pulse. Data is considered correct when the outputs of all five latch circuits
match. If they do not match, the previous value is retained. Upon reset, the noise canceller output
is initialized after the falling edge of the input capture signal has been sampled five times.
Accordingly, after the noise canceller function is enabled, pulses that have a pulse width five times
greater than the sampling clock will be recognized as input capture signals.
If the noise canceller circuit is not used, the input capture signal pulse width must be at least 2 or
2
Note: * Rewriting the NCS bit may cause an internal input capture signal to be generated.
Figure 9.10 shows a typical timing diagram for the noise canceller circuit. In this example, a high-
level input at the input capture pin is rejected as noise because its pulse width is less than five
sampling clock cycles.
216
Input capture
signal
Sampling clock
SUB
in order to ensure proper input capture operation.
Sampling clock
D
latch
Figure 9.9 Block Diagram of Noise Canceller Circuit
C
Q
t: Selected by bits CKS1, CKS0.
D
t
latch
C
Q
D
latch
C
Q
D
latch
C
Q
D
latch
C
Q
detection
Match
circuit
Noise
canceller
output