HD6473308RCP10V Renesas Electronics America, HD6473308RCP10V Datasheet - Page 112
HD6473308RCP10V
Manufacturer Part Number
HD6473308RCP10V
Description
MCU 5V 16K,PB-FREE 80-PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/330r
Datasheet
1.HD6473258P10V.pdf
(349 pages)
Specifications of HD6473308RCP10V
Core Size
8-Bit
Program Memory Size
16KB (16K x 8)
Oscillator Type
Internal
Core Processor
H8/300
Speed
10MHz
Number Of I /o
58
Program Memory Type
OTP
Ram Size
512 x 8
Operating Temperature
-20°C ~ 75°C
Package / Case
80-PLCC
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
10MHz
No. Of Timers
3
No. Of Pwm Channels
2
Digital Ic Case
RoHS Compliant
Controller Family/series
H8/330
Peripherals
ADC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply (vcc/vdd)
-
Eeprom Size
-
Data Converters
-
Peripherals
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6473308RCP10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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See section 4 “Exception Handling” and section 6, “Free-Running Timer Module” for details of the
free-running timer and interrupts.
Pins of port 6 can drive a single TTL load and a 90pF capacitive load when they are used as output
pins. They can also drive a Darlington pair. When they are used as input pins, they have
programmable MOS pull-ups.
Table 5-13 details the port 6 registers.
Table 5-13. Port 6 Registers
Name
Port 6 data direction register P6DDR
Port 6 data register
Port 6 Data Direction Register (P6DDR)—H’FFB9
Bit
Initial value
Read/Write
P6DDR is an 8-bit register that selects the direction of each pin in port 6. A pin functions as an
output pin if the corresponding bit in P6DDR is set to “1,” and as an input pin if the bit is cleared to
“0.”
Port 6 Data Register (P6DR)—H’FFBB
Bit
Initial value
Read/Write
P6DR is an 8-bit register containing the data for pins P6
output pins (P6DDR = "1") it reads the value in the P6DR latch, but for input pins (P6DDR = "0"),
it obtains the logic level directly from the pin, bypassing the P6DR latch. This also applies to pins
used for input and output of timer and interrupt signals.
P6
R/W
7
P6
W
DDR P6
7
0
7
0
7
R/W
6
P6
Abbreviation
P6DR
W
DDR P6
6
0
6
0
6
R/W
5
P6
W
DDR P6
5
0
5
0
5
Read/Write Initial value
W
R/W
R/W
97
4
P6
W
DDR P6
4
0
4
0
4
7
to P6
R/W
3
P6
W
DDR P6
3
0
3
0
3
H’00
H’00
0
. When the CPU reads P6DR, for
R/W
2
P6
W
DDR P6
2
0
2
0
2
R/W
1
P6
W
Address
H’FFB9
H’FFBB
DDR P6
1
0
1
0
1
R/W
0
P6
W
DDR
0
0
0
0
0
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