HD6473308RCP10V Renesas Electronics America, HD6473308RCP10V Datasheet - Page 80
HD6473308RCP10V
Manufacturer Part Number
HD6473308RCP10V
Description
MCU 5V 16K,PB-FREE 80-PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/330r
Datasheet
1.HD6473258P10V.pdf
(349 pages)
Specifications of HD6473308RCP10V
Core Size
8-Bit
Program Memory Size
16KB (16K x 8)
Oscillator Type
Internal
Core Processor
H8/300
Speed
10MHz
Number Of I /o
58
Program Memory Type
OTP
Ram Size
512 x 8
Operating Temperature
-20°C ~ 75°C
Package / Case
80-PLCC
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
10MHz
No. Of Timers
3
No. Of Pwm Channels
2
Digital Ic Case
RoHS Compliant
Controller Family/series
H8/330
Peripherals
ADC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply (vcc/vdd)
-
Eeprom Size
-
Data Converters
-
Peripherals
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6473308RCP10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Figure 4-3 shows a block diagram of the interrupt controller. Figure 4-4 is a flowchart showing the
operation of the interrupt controller and the sequence by which an interrupt is accepted. This
sequence is outlined below.
(1) The interrupt controller receives an interrupt request signal. Interrupt request signals can be
(2) When notified of an interrupt, the interrupt controller scans the interrupt signals in priority
(3) The interrupt controller accepts the interrupt if it is an NMI, or if it is another interrupt and the
(4) When an interrupt is accepted, after completion of the current instruction, the CPU pushes first
(5) The CPU sets the I bit in the CCR to “1,” masking all further interrupts except NMI during the
(6) The CPU generates the vector address of the interrupt and loads the word at this address into
(7) Execution of the software interrupt-handling routine starts from the address now in the pro-
(8) On the return from the interrupt-handling routine (RTE instruction), the CCR and PC are
The timing of this sequence is shown in Figure 4-5 for the case in which the program and vector
table are in on-chip ROM and the stack is in on-chip RAM.
order and selects the one with the highest priority. (See table 4-2 for the priority order.) Other
requested interrupts remain pending.
I bit in the CCR is cleared to “0.” If the interrupt is not an NMI and the I bit is set to “1,” the
interrupt is held pending.
the PC then the CCR onto the stack. The stacked PC indicates the address of the first
instruction that will be executed after the return. The stack pointer (R7) must indicate an even
address. See section 4.2.5, “Note on Stack Handling” for details.
interrupt-handling routine.
the program counter.
gram counter.
popped from the stack and execution of the interrupted program resumes.
generated by:
—
—
—
All interrupts except NMI have enable bits. The interrupt can be requested only when its
enable bit is set to "1."
A High-to-Low (or Low-to-High) transition of the NMI signal
A Low input (or High-to-Low transition) of one of the IRQ
An on-chip supporting module
65
0
to IRQ
7
signals
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