HD6473308RCP10V Renesas Electronics America, HD6473308RCP10V Datasheet - Page 150

• Manufacturer Part Number: HD6473308RCP10V
• Description: MCU 5V 16K,PB-FREE 80-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/330r

Specifications of HD6473308RCP10V

• Core Size: 8-Bit
• Program Memory Size: 16KB (16K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 10MHz
• Number Of I /o: 58
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-PLCC
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 10MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 2
• Digital Ic Case: RoHS Compliant
• Controller Family/series: H8/330
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply (vcc/vdd): -
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 5 – Input Edge Select C (IEDGC): This bit causes input capture C events to be recognized on
the selected edge of the input capture C signal (FTIC). In buffer mode (when BUFEA = “1”),
it also causes input capture A events to be recognized on the selected edge of FTIA.
Bit 5
IEDGC
Bit 4 – Input Edge Select D (IEDGD): This bit causes input capture D events to be recognized on
the selected edge of the input capture D signal (FTID). In the buffer mode (when BUFEB = “1”),
it also causes input capture B events to be recognized on the selected edge of FTIB.
Bit 4
IEDGD
Bit 3 – Buffer Enable A (BUFEA): This bit selects whether to use ICRC as a buffer register for
ICRA.
Bit 3
BUFEA
Bit 2 – Buffer Enable B (BUFEB): This bit selects whether to use ICRD as a buffer register for
ICRB.
Bit 2
BUFEB
Bits 1 and 0 – Clock Select (CKS1 and CKS0): These bits select external clock input or one of
three internal clock sources for the FRC. External clock pulses are counted on the rising edge.
0
1
0
1
0
1
0
1
Description
Input capture C events are recognized on the falling edge of FTIC.
Input capture C events are recognized on the rising edge of FTIC.
Description
Input capture D events are recognized on the falling edge of FTID.
Input capture D events are recognized on the rising edge of FTID.
Description
ICRC is used for input capture C.
ICRC is used as a buffer register for input capture A. Input C is not captured.
Description
ICRD is used for input capture D.
ICRD is used as a buffer register for input capture B. Input D is not captured.
135
(Initial value)
(Initial value)
(Initial value)
(Initial value)