HD6473308RCP10V Renesas Electronics America, HD6473308RCP10V Datasheet - Page 157
HD6473308RCP10V
Manufacturer Part Number
HD6473308RCP10V
Description
MCU 5V 16K,PB-FREE 80-PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/330r
Datasheet
1.HD6473258P10V.pdf
(349 pages)
Specifications of HD6473308RCP10V
Core Size
8-Bit
Program Memory Size
16KB (16K x 8)
Oscillator Type
Internal
Core Processor
H8/300
Speed
10MHz
Number Of I /o
58
Program Memory Type
OTP
Ram Size
512 x 8
Operating Temperature
-20°C ~ 75°C
Package / Case
80-PLCC
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
10MHz
No. Of Timers
3
No. Of Pwm Channels
2
Digital Ic Case
RoHS Compliant
Controller Family/series
H8/330
Peripherals
ADC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply (vcc/vdd)
-
Eeprom Size
-
Data Converters
-
Peripherals
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6473308RCP10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(3) Output Timing: When a compare-match occurs, the logic level selected by the output level
bit (OLVLA or OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 6-
10 shows the timing of this operation for compare-match A.
(4) FRC Clear Timing: If the CCLRA bit in the TCSR is set to “1,” the FRC is cleared when
compare-match A occurs. Figure 6-11 shows the timing of this operation.
6.4.3 Input Capture Timing
(1) Input Capture Timing: An internal input capture signal is generated from the rising or falling
edge of the signal at the input capture pin FTIx (x = A, B, C, D), as selected by the corresponding
IEDGx bit in TCR. Figure 6-12 shows the usual input capture timing when the rising edge is
selected (IEDGx = “1”).
Ø
Internal compare-
match A signal
FRC
Ø
FRC
OCRA
Internal compare-
match A signal
OLVLA
FTOA
*
Cleared by software
Figure 6-11. Clearing of FRC by Compare-Match A
N
N
Figure 6-10. Timing of Output Compare A
N
N + 1
142
Clear
*
N
N
H'0000
Figure 6-10
N + 1
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