HD6473308RCP10V Renesas Electronics America, HD6473308RCP10V Datasheet - Page 39

• Manufacturer Part Number: HD6473308RCP10V
• Description: MCU 5V 16K,PB-FREE 80-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/330r

Specifications of HD6473308RCP10V

• Core Size: 8-Bit
• Program Memory Size: 16KB (16K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 10MHz
• Number Of I /o: 58
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-PLCC
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 10MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 2
• Digital Ic Case: RoHS Compliant
• Controller Family/series: H8/330
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply (vcc/vdd): -
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.4.2 System Control Register (SYSCR) – H’FFC4
By setting or clearing the lower two bits of the system control register, software can enable or
disable the on-chip RAM and dual-port RAM.
The other bits in the system control register concern the software standby mode and the valid edge
of the NMI signal. These bits will be described in section 4, “Exception Handling” and section 14,
“Power-Down State.”
Bit
Initial value
Read/Write
Bit 1—Dual-Port RAM Enable (DPME): In the single-chip mode, this bit enables or disables the
dual-port RAM. When enabled, the dual-port RAM can be accessed by both an external (master)
CPU and the on-chip (slave) CPU. When disabled, the dual-port RAM can be accessed only by the
on-chip CPU.
This bit affects the usage of ports 3, 8, and 9.
Bit 1
DPME
Bit 0—RAM Enable (RAME): This bit enables or disables the 512-byte on-chip RAM. When
enabled, the on-chip RAM occupies addresses H’FD80 to H’FF7F of the address space. When the
on-chip RAM is disabled, accesses to these addresses are directed off-chip.
The RAME bit is initialized to "1" by a reset, enabling the on-chip RAM. The setting of the
RAME bit is not altered in the sleep mode or software standby mode. It should be cleared to "0"
before entering the hardware standby mode. See section 14, "Power-Down State."
Bit 0
RAME
0
1
0
1
Description
The dual-port RAM is disabled. (Initial state)
Single-chip mode: The dual-port RAM is enabled (slave mode).
Expanded modes: The dual-port RAM is disabled (but can be accessed by the on-chip
Description
The on-chip RAM is disabled.
The on-chip RAM is enabled.
SSBY
R/W
7
0
STS2
R/W
6
0
CPU).
STS1
R/W
5
0
STS0
R/W
22
4
0
—
—
3
1
NMIEG DPME
R/W
2
0
(Initial state)
R/W
1
0
RAME
R/W
0
1