HD6473308RCP10V Renesas Electronics America, HD6473308RCP10V Datasheet - Page 176
HD6473308RCP10V
Manufacturer Part Number
HD6473308RCP10V
Description
MCU 5V 16K,PB-FREE 80-PLCC
Manufacturer
Renesas Electronics America
Series
H8® H8/330r
Datasheet
1.HD6473258P10V.pdf
(349 pages)
Specifications of HD6473308RCP10V
Core Size
8-Bit
Program Memory Size
16KB (16K x 8)
Oscillator Type
Internal
Core Processor
H8/300
Speed
10MHz
Number Of I /o
58
Program Memory Type
OTP
Ram Size
512 x 8
Operating Temperature
-20°C ~ 75°C
Package / Case
80-PLCC
No. Of I/o's
58
Ram Memory Size
512Byte
Cpu Speed
10MHz
No. Of Timers
3
No. Of Pwm Channels
2
Digital Ic Case
RoHS Compliant
Controller Family/series
H8/330
Peripherals
ADC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply (vcc/vdd)
-
Eeprom Size
-
Data Converters
-
Peripherals
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6473308RCP10V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Accordingly, when the timer count matches one of the time constants, the compare-match signal is
not generated until the next period of the clock source. Figure 7-5 shows the timing of the setting
of the compare-match flags.
(2) Timing of Compare-Match Flag (CMFA or CMFB) Clearing: The compare-match flag
CMFA or CMFB is cleared when the CPU writes a “0” in this bit.
(3) Output Timing: When a compare-match event occurs, the timer output (TMO0 or TMO1)
changes as specified by the output select bits (OS3 to OS0) in the TCSR. Depending on these bits,
the output can remain the same, change to “0,” change to “1,” or toggle. If compare-match A and
B occur simultaneously, the higher priority compare-match determines the output level. See item
(4) in section 7.6, “Application Notes” for details.
TCOR
TCNT
Internal
compare-match
signal
CMF
Ø
f
Ø
CMFA
or CMFB
Figure 7-6. Clearing of Compare-Match Flags
Figure 7-5. Setting of Compare-Match Flags
Write cycle: CPU writes "0" in CMFA or CMFB
T
N
N
1
162
T
2
T
3
N + 1
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