HD6473308RCP10V Renesas Electronics America, HD6473308RCP10V Datasheet - Page 245

• Manufacturer Part Number: HD6473308RCP10V
• Description: MCU 5V 16K,PB-FREE 80-PLCC
• Manufacturer: Renesas Electronics America
• Series: H8® H8/330r

Specifications of HD6473308RCP10V

• Core Size: 8-Bit
• Program Memory Size: 16KB (16K x 8)
• Oscillator Type: Internal
• Core Processor: H8/300
• Speed: 10MHz
• Number Of I /o: 58
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-PLCC
• No. Of I/o's: 58
• Ram Memory Size: 512Byte
• Cpu Speed: 10MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 2
• Digital Ic Case: RoHS Compliant
• Controller Family/series: H8/330
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply (vcc/vdd): -
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit 0 – Slave Write Mode Flag (SWMF): This bit indicates when the dual-port RAM is in the
slave write mode. The H8/300 CPU should check that this bit is set to “1” before writing to parallel
communication data registers 1 to 14. The master CPU cannot write in those registers while this bit
is set to “1.”
Bit 0
SWMF
11.3 Usage
The dual-port RAM has a simple protocol for controlling the use of the data registers and parallel
communication data bus. The basic rule is that when either CPU writes to the dual-port RAM, it
should write to PCDR0 first and PCDR14 last. Conversely, in reading the dual-port RAM, the
CPU should read PCDR14 first and PCDR0 last.
Procedures for data transfer in both directions are given below. Figure 11-3 shows a timing chart.
11.3.1 Data Transfer from Master CPU to H8/300 CPU
The following procedure should be used when the master CPU sends data to the H8/300 CPU via
the dual-port RAM:
(1) The master CPU writes the first byte of data in PCDR0. If the dual-port RAM is not currently
(2) The master CPU reads the PCCSR and checks MWMF. If MWMF is set to “1,” the master
(3) The master CPU writes data in PCDR1 to PCDR13 as required, then writes the last byte in
0
1
in the slave write mode, MWMF is set to "1," placing it in the master write mode and
preventing the H8/300 CPU from writing in PCDR1 to PCDR14.
CPU may continue writing in PCDR1 to PCDR14. If MWMF is cleared to "0," the dual-port
RAM is presumably in the slave write mode.
PCDR14. This sets the master write end flag (MWEF) to “1,” notifying the H8/300 CPU that
the master CPU has finished writing. If EMWI is set to “1,” a master write end interrupt is
requested.
Description
This bit is cleared to “0” when the master CPU reads PCDR0.
The dual-port RAM is not in the slave write mode. The H8/300
CPU should avoid writing in PCDR1 to PCDR14.
This bit is set to “1” if the H8/300 CPU writes to PCDR0 while the
MWMF flag is cleared to “0.” The dual-port RAM is in the slave
write mode. Only the H8/300 CPU can write in PCDR1 to PCDR14.
234
(Initial state)