HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 164

• Manufacturer Part Number: HD6417750SF167V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF167V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 3 Memory Management Unit (MMU)
• URB: UTLB replace boundary. Bits that indicate the UTLB entry boundary at which
• URC: UTLB replace counter. Random counter for indicating the UTLB entry for which
• SQMD: Store queue mode bit. Specifies the right of access to the store queues.
• SV: Single virtual mode bit. Bit that switches between single virtual memory mode and
• TI: TLB invalidation bit. Writing 1 to this bit invalidates (clears to 0) all valid UTLB/ITLB
• AT: Address translation enable bit. Specifies MMU enabling or disabling.
Rev.7.00 Oct. 10, 2008 Page 78 of 1074
REJ09B0366-0700
Ensure that values for which “Setting prohibited” is indicated in the above table are not set at
the discretion of software. After a power-on or manual reset the LRUI bits are initialized to 0,
and therefore a prohibited setting is never made by a hardware update.
replacement is to be performed. Valid only when URB > 0.
replacement is to be performed with an LDTLB instruction. URC is incremented each time the
UTLB is accessed. When URB > 0, URC is reset to 0 when the condition URC = URB occurs.
Also note that, if a value is written to URC by software which results in the condition URC >
URB, incrementing is first performed in excess of URB until URC = H'3F. URC is not
incremented by an LDTLB instruction.
0: User/privileged access possible
1: Privileged access possible (address error exception in case of user access)
multiple virtual memory mode.
0: Multiple virtual memory mode
1: Single virtual memory mode
When this bit is changed, ensure that 1 is also written to the TI bit.
bits. This bit always returns 0 when read.
0: MMU disabled
1: MMU enabled
ITLB entry 0 is updated
ITLB entry 1 is updated
ITLB entry 2 is updated
ITLB entry 3 is updated
Other than the above
[5]
1
0
*
*
Setting prohibited
[4]
1
*
0
*
[3]
1
*
*
0
LRUI
[2]
*
1
0
*
[1]
*
1
*
0
[0]
*
*
1
0