HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 167

• Manufacturer Part Number: HD6417750SF167V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF167V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

The area from H'E000 0000 to H'E3FF FFFF comprises addresses for accessing the store queues
(SQs). When the MMU is disabled (MMUCR.AT = 0), the SQ access right is specified by the
MMUCR.SQMD bit. For details, see section 4.7, Store Queues.
The area from H'F000 0000 to H'F0FF FFFF is used for direct access to the instruction cache
address array. For details, see section 4.5.1, IC Address Array.
The area from H'F100 0000 to H'F1FF FFFF is used for direct access to the instruction cache data
array. For details, see section 4.5.2, IC Data Array.
The area from H'F200 0000 to H'F2FF FFFF is used for direct access to the instruction TLB
address array. For details, see section 3.7.1, ITLB Address Array.
H'E000 0000
H'E400 0000
H'F000 0000
H'F100 0000
H'F200 0000
H'F300 0000
H'F400 0000
H'F500 0000
H'F600 0000
H'F700 0000
H'F800 0000
H'FC00 0000
Figure 3.4 P4 Area
Instruction TLB data arrays 1 and 2
Unified TLB data arrays 1 and 2
Instruction cache address array
Operand cache address array
Instruction TLB address array
Instruction cache data array
Operand cache data array
Unified TLB address array
Control register area
Reserved area
Reserved area
Store queue
Section 3 Memory Management Unit (MMU)
Rev.7.00 Oct. 10, 2008 Page 81 of 1074
REJ09B0366-0700