HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 181

• Manufacturer Part Number: HD6417750SF167V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF167V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

procedure is known as hardware ITLB miss handling. If the necessary address translation
information is not found in the UTLB search, an instruction TLB miss exception is generated and
processing passes to software.
3.5.5
When 1- or 4-Kbyte pages are recorded in TLB entries, a synonym problem may arise. The
problem is that, when a number of virtual addresses are mapped onto a single physical address, the
same physical address data is recorded in a number of cache entries, and it becomes impossible to
guarantee data integrity. This problem does not occur with the instruction TLB or instruction
cache. In the SH-4, entry specification is performed using bits [13:5] of the virtual address in order
to achieve fast operand cache operation. However, bits [13:10] of the virtual address in the case of
a 1-Kbyte page, and bits [13:12] of the virtual address in the case of a 4-Kbyte page, are subject to
address translation. As a result, bits [13:10] of the physical address after translation may differ
from bits [13:10] of the virtual address.
Consequently, the following restrictions apply to the recording of address translation information
in UTLB entries.
1. When address translation information whereby a number of 1-Kbyte page UTLB entries are
2. When address translation information whereby a number of 4-Kbyte page UTLB entries are
3. Do not use 1-Kbyte page UTLB entry physical addresses with UTLB entries of a different
4. Do not use 4-Kbyte page UTLB entry physical addresses with UTLB entries of a different
The above restrictions apply only when performing accesses using the cache. When cache index
mode is used, VPN [25] is used for the entry address instead of VPN [13], and therefore the above
restrictions apply to VPN [25].
Note: When multiple items of address translation information use the same physical memory to
translated into the same physical address is recorded in the UTLB, ensure that the VPN [13:10]
values are the same.
translated into the same physical address is recorded in the UTLB, ensure that the VPN [13:12]
values are the same.
page size.
page size.
provide for future SuperH RISC engine family expansion, ensure that the VPN [20:10]
values are the same. Also, do not use the same physical address for address translation
information of different page sizes.
Avoiding Synonym Problems
Section 3 Memory Management Unit (MMU)
Rev.7.00 Oct. 10, 2008 Page 95 of 1074
REJ09B0366-0700