HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 342

MPU 3V 16K PB-FREE 208-QFP

HD6417750SF167V

Manufacturer Part Number

HD6417750SF167V

Description

MPU 3V 16K PB-FREE 208-QFP

Manufacturer

Renesas Electronics America

Series

SuperH® SH7750r

Datasheet

1.D6417750RBP240DV.pdf (1164 pages)

Specifications of HD6417750SF167V

Core Processor

SH-4

Core Size

32-Bit

Speed

167MHz

Connectivity

EBI/EMI, FIFO, SCI, SmartCard

Peripherals

DMA, POR, WDT

Number Of I /o

28

Program Memory Type

ROMless

Ram Size

24K x 8

Voltage - Supply (vcc/vdd)

1.6 V ~ 2 V

Oscillator Type

External

Operating Temperature

-20°C ~ 75°C

Package / Case

208-QFP

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Eeprom Size

-

Program Memory Size

-

Data Converters

-

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Bonase Electronics (HK) Co., Limited

Part Number:

HD6417750SF167V

Manufacturer:

INTERSIL

Quantity:

18 720

Company:

BOSTOCK HK LIMITED

BOSTOCK HK LIMITED

Part Number:

HD6417750SF167V

Manufacturer:

Renesas Electronics America

Quantity:

10 000

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Section 8 Pipelining

Notes: 1. See table 8.1 for the instruction groups.

Rev.7.00 Oct. 10, 2008 Page 256 of 1074

REJ09B0366-0700

Functional

Category

Double-

precision

floating-point

instructions

FPU system

control

instructions

Graphics

acceleration

instructions

2. Latency “L1/L2...”: Latency corresponding to a write to each register, including

3. Branch latency: Interval until the branch destination instruction is fetched

MACH/MACL/FPSCR.

Example: MOV.B @Rm+, Rn “1/2”: The latency for Rm is 1 cycle, and the latency for

No.

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

Instruction

FNEG

FSQRT

FSUB

FTRC

LDS

LDS

LDS.L

LDS.L

STS

STS

STS.L

STS.L

FMOV

FMOV

FMOV

FMOV

FMOV

FMOV

FMOV

FMOV

FMOV

FIPR

FRCHG

FSCHG

FTRV

Rn is 2 cycles.

DRn

DRn

DRm,DRn

DRm,FPUL

Rm,FPUL

Rm,FPSCR

@Rm+,FPUL

@Rm+,FPSCR

FPUL,Rn

FPSCR,Rn

FPUL,@-Rn

FPSCR,@-Rn

DRm,XDn

XDm,DRn

XDm,XDn

@Rm,XDn

@Rm+,XDn

@(R0,Rm),XDn

XDm,@Rn

XDm,@-Rm

XDm,@(R0,Rn)

FVm,FVn

XMTRX,FVn

Instruc-

tion

Group

LS

FE

FE

FE

LS

CO

CO

CO

LS

CO

CO

CO

LS

LS

LS

LS

LS

LS

LS

LS

LS

FE

FE

FE

FE

Issue

Rate

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Latency

0

(23, 24)/

25

(7, 8)/9

4/5

1

4

1/2

1/4

3

3

1/1

1/1

0

0

0

2

1/2

2

1

1/1

1

4/5

1/4

1/4

(5, 5, 6,

7)/8

Execu-

tion

Pattern Stage Start Cycles

#1

#41

#39

#38

#1

#32

#2

#33

#1

#1

#2

#2

#1

#1

#1

#2

#2

#2

#2

#2

#2

#42

#36

#36

#43

—

—

—

F3

F1

F1

F1

F1

—

F1

—

F1

—

—

—

—

—

—

—

—

—

—

—

F1

—

—

F0

F1

—

2

21

2

2

2

—

3

—

3

—

—

—

—

—

—

—

—

—

—

—

—

—

3

—

—

2

3

Lock

—

22

3

2

6

2

—

3

—

3

—

—

—

—

—

—

—

—

—

—

—

—

—

1

—

—

4

4

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