HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 719

• Manufacturer Part Number: HD6417750SF167V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF167V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

7. DTR format
8. Data transfer end request
9. Request queue clearance
10. DBREQ assertion
a. The DDT module processes DTR.ID, DTR.MD, and DTR.SZ as follows.
a. A data transfer end request (DTR.ID = 00, MD ≠ 00, SZ = 111) cannot be accepted during
b. When a transfer end request (DTR.ID = 00, MD ≠ 00, SZ = 111) is accepted, the values set
a. When settings of DTR.ID = 00, DTR.MD = 10, and SZ = 110 are accepted by the DDT in
b. In case 4-d, the DMAC freeze state can be cleared.
c. When settings of DMAOR.DDT = 1, DTR.ID = 00, DTR.MD = 10, and SZ = 110 are
a. After DBREQ is asserted, do not assert DBREQ again until BAVL is asserted, as this will
b. The BAVL assertion period due to DBREQ assertion is one cycle.
c. It takes one cycle for DBREQ to be accepted by the DMAC after being asserted by an
When DTR.ID= 00
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•
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When DTR.ID ≠ 00
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channel 0 DMA transfer. Therefore, if edge detection and burst mode are set for channel 0,
transfer cannot be ended midway.
in CHCR0, SAR0, DAR0, and DMATCR0 are retained. With the SH7750, execution
cannot be restarted from an external device in this case. To restart execution in the
SH7750S and SH7750R, set CHCR0.DE = 1 with an MOV instruction.
normal data transfer mode, DDT channel 0 requests and channel 1 to 3 request queues are
all cleared. All external requests held on the DMAC side are also cleared.
accepted by the DDT in case 11, the DMAC freeze state can be cleared.
result in a discrepancy between the number of DBREQ and BAVL assertions.
If a row address miss occurs in a read or write in the non-precharged bank during
synchronous DRAM access, BAVL is asserted for a number of cycles in accordance with
the RAS precharge interval set in BSC.MCR.TCP.
external device. If a row address miss occurs at this time in a read or write in the non-
precharged bank during synchronous DRAM access, and BAVL is asserted, the DBREQ
signal asserted by the external device is ignored. Therefore, BAVL is not asserted again
due to this signal.
MD = 00, SZ ≠ 101, 110: Handshake protocol using the data bus
MD ≠ 00, SZ = 111: CHCR0.DE = 0 setting (DMA transfer end request)
MD ≠ 10, SZ = 110: DDT request queue clear
Transfer request to channels 1—3 (items other than ID ignored)
Section 14 Direct Memory Access Controller (DMAC)
Rev.7.00 Oct. 10, 2008 Page 633 of 1074
REJ09B0366-0700