HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 729

• Manufacturer Part Number: HD6417750SF167V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF167V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
Bit 19—DREQ Select (DS): Specifies either low level detection or falling edge detection as the
sampling method for the DREQ pin used in external request mode.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in
CHCR0–CHCR7. For details of the settings, see the description of the DS bit in section 14.2.4,
DMA Channel Control Registers 0−3 (CHCR0−CHCR3).
Bit 18—Request Check Level (RL): Selects whether the DRAK signal (that notifies an external
device of the acceptance of DREQ) is an active-high or active-low output.
This bit is valid only in CHCR0 and CHCR1 in normal mode, and is invalid in DDT mode. For
details of the settings, see the description of the RL bit in section 14.2.4, DMA Channel Control
Registers 0−3 (CHCR0−CHCR3).
Bit 17—Acknowledge Mode (AM): In dual address mode, selects whether DACK is output in the
data read cycle or write cycle. In single address mode, DACK is always output regardless of the
setting of this bit.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in
CHCR0–CHCR7. (DDT mode: TDACK) For details of the settings, see the description of the AM
bit in section 14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3).
Bit 16—Acknowledge Level (AL): Specifies the DACK (acknowledge) signal as active-high or
active-low.
This bit is valid only in CHCR0 and CHCR1 in normal mode, and is invalid in DDT mode. For
details of the settings, see the description of the AL bit in section 14.2.4, DMA Channel Control
Registers 0−3 (CHCR0−CHCR3).
Bits 15 and 14—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify
incrementing/decrementing of the DMA transfer destination address. The specification of these
bits is ignored when data is transferred from external memory to an external device in single
address mode. For details of the settings, see the description of the DM1 and DM0 bits in section
14.2.4, DMA Channel Control Registers 0−3 (CHCR0−CHCR3).
Bits 13 and 12—Source Address Mode 1 and 0 (SM1, SM0): These bits specify
incrementing/decrementing of the DMA transfer source address. The specification of these bits is
ignored when data is transferred from an external device to external memory in single address
mode. For details of the settings, see the description of the SM1 and SM0 bits in section 14.2.4,
DMA Channel Control Registers 0−3 (CHCR0−CHCR3).
Rev.7.00 Oct. 10, 2008 Page 643 of 1074
REJ09B0366-0700