HD6417750SF167V Renesas Electronics America, HD6417750SF167V Datasheet - Page 734

• Manufacturer Part Number: HD6417750SF167V
• Description: MPU 3V 16K PB-FREE 208-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750SF167V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 167MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
14.8.3
When the DMAC is set up for four-channel external request acceptance in DDT mode
(DMAOR.DBL = 0), the ID [1:0] bits are used to notify the external device of the DMAC channel
that is to be used. For more details, see section 14.5, On-Demand Data Transfer Mode (DDT
Mode).
When the DMAC is set up for eight-channel external request acceptance in DDT mode
(DMAOR.DBL = 1), the ID [1:0] bits and the simultaneous (on the timing of TDACK assertion)
assertion of ID2 from the BAVL (data bus available) pin are used to notify the external device of
the DMAC channel that is to be used (see table 14.15).
When the DMAC is set up for eight-channel external request acceptance in DDT mode
(DMAOR.DBL = 1), it is important to note that the BAVL pin has the two functions as shown in
table 14.16.
Table 14.15 Notification of Transfer Channel in Eight-Channel DDT Mode
BAVL/ID2
0
Table 14.16 Function of BAVL
TDACK = High
TDACK = Low
Rev.7.00 Oct. 10, 2008 Page 648 of 1074
REJ09B0366-0700
1
Transfer Channel Notification in DDT Mode
ID[1:0]
00
01
10
11
00
01
10
11
Function of BAVL
Bus available
Notification of channel number (ID2)
Transfer Channel
CH4
CH5
CH6
CH7
CH0
CH1
CH2
CH3