UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 210

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
P61
P62
P63
P70 to P73,
P74
P75
P120
P121
P122
P123
P124
P125
Notes 1. During I
Remarks 1. ×:
Pin Name
Note 4
Note 4
Note 3
,
2. When using an input compliant with the SMBus specifications in I
3. 44-pin and 48-pin products only
4. 48-pin products only
5. When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or subsystem
6. Clear RSTM bit (bit 5 of RSTMASK register) to 0 when using P125 as an external reset input (RESET).
Table 4-18. Settings of Port Mode Register and Output Latch When Using Alternate Function
2. Functions in parentheses ( ) can be assigned by setting MUXSEL register.
POM6 register (refer to 4.3 (5) Port output mode register 6 (POM6)).
buffer by using PIM6 register (refer to 4.3 (4) Port input mode register 6 (PIM6)).
clock (XT1, XT2), or to input an external clock for the main system clock (EXCLK) or subsystem clock
(EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or external clock input mode must be set by using
OSCCTL register (for details, refer to 5.3 (1) Clock operation mode select register (OSCCTL) and (3)
Setting of operation mode for subsystem clock pin). The reset value of OSCCTL is 00H (all of the P121
to P124 pins are Input port pins).
SDAA0
SI11
INTP10
SO11
INTP9
INTP8
KR0 to KR3, KR4
INTP0
EXLVI
(SO11)
X1
TOOLC0
X2
EXCLK
TOOLD0
XT1
XT2
EXCLKS
RESET
PM××: Port mode register
P××:
Note 5
Note 5
Note 5
Note 5
Note 3
2
C communication, set SCLA0 and SDAA0 to N-ch open drain output (V
Note 3
Notes 1, 2
Note 5
Note 6
Note 5
Don’t care
Port output latch
Function Name
Note 4
, KR5
Alternate Function
Note 4
(78K0/KC2-L) (3/3)
I/O
Input
Input
Output
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Input
Input
I/O
−
−
−
−
CSISEL = 0
CSISEL = 0
CSISEL = 1
MUXSEL
2
C communication, select the SMBus input
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
CHAPTER 4 PORT FUNCTIONS
DD
PM××
tolerance) mode by using
0
1
1
0
1
1
1
1
1
0
×
×
×
×
×
×
×
×
×
P××
1
×
×
0
×
×
×
×
×
0
×
×
×
×
×
×
×
×
×
196