UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 529

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
15.5.9 Address match detection method
address has been set to the slave address register 0 (SVA0) and when the address set to the SVA0 register matches the
slave address sent by the master device, or when an extension code has been received.
15.5.10 Error detection
register (IICA) of the transmitting device, so the IICA data prior to transmission can be compared with the transmitted IICA
data to enable detection of transmission errors. A transmission error is judged as having occurred when the compared
data values do not match.
15.5.11 Extension code
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
(5) Stop condition detection
In I
Address match can be detected automatically by hardware. An interrupt request (INTIICA0) occurs when a local
In I
(1) When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code reception flag (EXC0)
(2) If “11110××0” is set to the SVA0 register by a 10-bit address transfer and “11110××0” is transferred from the master
(3) Since the processing after the interrupt request occurs differs according to the data that follows the extension code,
2
2
C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address.
INTIICA0 is generated when a stop condition is detected (only when SPIE0 = 1).
C bus mode, the status of the serial data bus (SDAA0) during data transmission is captured by the IICA shift
is set to 1 for extension code reception and an interrupt request (INTIICA0) is issued at the falling edge of the
eighth clock. The local address stored in the slave address register 0 (SVA0) is not affected.
device, the results are as follows. Note that INTIICA0 occurs at the falling edge of the eighth clock.
• Higher four bits of data match: EXC0 = 1
• Seven bits of data match:
Remark
such processing is performed by software.
If the extension code is received while a slave device is operating, then the slave device is participating in
communication even if its address does not match.
For example, after the extension code is received, if you do not wish to operate the target device as a slave device,
set bit 6 (LREL0) of the IICA control register 0 (IICACTL0) to 1 to set the standby mode for the next communication
operation.
Remark
Slave Address
EXC0: Bit 5 of IICA status register 0 (IICAS0)
COI0: Bit 4 of IICA status register 0 (IICAS0)
For extension codes other than the above, refer to THE I
0 0 0 0 0 0 0
1 1 1 1 0 x x
1 1 1 1 0 x x
Table 15-3. Bit Definitions of Main Extension Code
R/W Bit
COI0 = 1
0
0
1
General call address
10-bit slave address specification (for address authentication)
after address match)
10-bit slave address specification (for read command issuance
CHAPTER 15 SERIAL INTERFACE IICA
2
Description
C-BUS SPECIFICATION published by NXP.
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