UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 510

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Caution When bit 3 (TRC0) of the IICA status register 0 (IICAS0) is set to 1 (transmission status), bit 5
Cautions concerning set timing
• For master reception:
• For master transmission: A stop condition cannot be generated normally during the acknowledge period.
• Cannot be set to 1 at the same time as start condition trigger (STT0).
• The SPT0 bit can be set to 1 only when in master mode.
• When the WTIM0 bit has been cleared to 0, if the SPT0 bit is set to 1 during the wait period that follows output of
• Setting the SPT0 bit to 1 and then setting it again before it is cleared to 0 is prohibited.
Condition for clearing (SPT0 = 0)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
Remark
eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. The WTIM0
bit should be changed from 0 to 1 during the wait period following the output of eight clocks, and the SPT0 bit should
be set to 1 during the wait period that follows the output of the ninth clock.
SPT0
0
1
(WREL0) of the IICACTL0 register is set to 1 during the ninth clock and wait is canceled,
after which the TRC0 bit is cleared (reception status) and the SDAA0 line is set to high
impedance. Release the wait performed while the TRC0 bit is 1 (transmission status) by
writing to the IICA shift register.
Bit 0 (SPT0) becomes 0 when it is read after data setting.
Stop condition is not generated.
Stop condition is generated (termination of master device’s transfer).
Figure 15-5. Format of IICA Control Register 0 (IICACTL0) (4/4)
Cannot be set to 1 during transfer.
Can be set to 1 only in the waiting period when ACKE0 has been cleared to 0 and slave
has been notified of final reception.
Therefore, set it during the wait period that follows output of the ninth clock.
Stop condition trigger
Condition for setting (SPT0 = 1)
• Set by instruction
CHAPTER 15 SERIAL INTERFACE IICA
496