UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 812

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
C.2 Revision History of Preceding Editions
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
2nd Edition
Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition.
Remark “Classification” in the above table classifies revisions as follows.
Edition
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d):
Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Modification of P60 and P61 pins alternate function in the 78K0/KY2-L and 78K0/KA2-L
1.1 Features
• Modification of description of low power consumption
• Modification of description and table of serial interface
• Modification of 10-bit resolution A/D conversion
Modification of 1.2 Ordering Information
Modification of pin configurations in 1.3.1 78K0/KY2-L and 1.3.2 78K0/KA2-L
Modification of 1.3.3 78K0/KB2-L and 1.3.4 78K0/KC2-L
Modification of 1.4.1 78K0/KY2-L to 1.4.4 78K0/KC2-L
Modification of 1.5 Outline of Functions
Modification of 2.1.3 78K0/KB2-L and 2.1.4 78K0/KC2-L
Modification of table of pins in 2.2.2 P10 to P17 (port 1)
Modification of 2.2.10 (b) IC
Modification of Table 2-4 Pin I/O Circuit Types (78K0/KB2-L)
Modification of Table 2-5 Pin I/O Circuit Types (78K0/KC2-L) (1/2)
Modification of Table 3-4 Vector Table
Addition of 8-bit A/D conversion result register L and modification of serial I/O shift register
10, serial operation mode register 10, serial clock selection register 10, and transmit buffer
register 10 in Table 3-6 Special Function Register List
Modification of Table 4-4 Port Functions (78K0/KB2-L)
Modification of Table 4-5 Port Functions (78K0/KC2-L) (1/2)
Modification of Note in Table 4-6 Port Configuration
Modification of table of pins and description in 4.2.2 Port 1
Modification of Table 4-7 Setting Functions of P10/ANI8/AMP1-, P12/ANI10/AMP1+
Pins
Modification of Figure 4-4 Block Diagram of P10
Modification of Figure 4-5 Block Diagram of P11
Modification of Figure 4-6 Block Diagram of P12
Modification of Table 4-9 Setting Functions of P20/ANI0/AMP0-, P22/ANI2/AMP0+ Pins
Modification of Figure 4-19 Block Diagram of P40
Addition of Figure 4-20 Block Diagram of P41 and modification of Figure 4-21 Block
Diagram of P42
Modification of Figure 4-27 Block Diagram of P120 (2/2)
Modification of Note in 4.3 (7) A/D port configuration registers 0, 1 (ADPC0, ADPC1)
Description
APPENDIX C REVISION HISTORY
Throughout
CHAPTER 1
OUTLINE
CHAPTER 2 PIN
FUNCTIONS
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 4 PORT
FUNCTIONS
Chapter
(1/8)
798