UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 680

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UPD78F0551MA-FAA-AX

Manufacturer Part Number
UPD78F0551MA-FAA-AX
Description
MCU 8BIT 16-SSOP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2-Lr
Datasheet

Specifications of UPD78F0551MA-FAA-AX

Core Processor
78K/0
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
9
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
78K0/Kx2-L
21.2 Configuration of Power-on-Clear Circuit
21.3 Operation of Power-on-Clear Circuit
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
The block diagram of the power-on-clear circuit is shown in Figure 21-1.
• An internal reset signal is generated on power application. When the supply voltage (V
• The supply voltage (V
The timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is shown
below.
Caution If the LVI default function enabled is set by using an option byte, the reset signal is not released
voltage (V
internal reset signal is generated.
until the supply voltage (V
POR
= 1.61 V ±0.09 V), the reset status is released.
V
DD
DD
) and POC detection voltage (V
Figure 21-1. Block Diagram of Power-on-Clear Circuit
Reference
voltage
source
DD
) exceeds 1.91 V ±0.1 V.
+
V
DD
PDR
= 1.59 V ±0.09 V) are compared. When V
CHAPTER 21 POWER-ON-CLEAR CIRCUIT
Internal reset signal
DD
) exceeds POC detection
DD
< V
PDR
, the
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