UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 508

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Notes 1. The signal of this bit is invalid while the IICE0 bit is 0. Set this bit during that period.
If the WUP bit of the IICA control register 1 (IICACTL1) is 1, no stop condition interrupt will be generated even if
SPIE0 = 1.
Condition for clearing (SPIE0 = 0)
• Cleared by instruction
• Reset
An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of
this bit. The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is
inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local
address, a wait is inserted at the falling edge of the ninth clock after an acknowledge (ACK) is issued. However,
when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock.
Condition for clearing (WTIM0 = 0)
• Cleared by instruction
• Reset
Condition for clearing (ACKE0 = 0)
• Cleared by instruction
• Reset
WTIM0
SPIE0
ACKE0
Notes 1, 2
0
1
0
1
0
1
Note 1
Note 1
2. The set value is invalid during address transfer and if the code is not an extension code.
When the device serves as a slave and the addresses match, an acknowledgment is generated
regardless of the set value.
Disable
Enable
Interrupt request is generated at the eighth clock’s falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device.
Interrupt request is generated at the ninth clock’s falling edge.
Master mode: After output of nine clocks, clock output is set to low level and wait is set.
Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device.
Disable acknowledgment.
Enable acknowledgment. During the ninth clock period, the SDAA0 line is set to low level.
Figure 15-5. Format of IICA Control Register 0 (IICACTL0) (2/4)
Enable/disable generation of interrupt request when stop condition is detected
Control of wait and interrupt request generation
Acknowledgment control
Condition for setting (SPIE0 = 1)
• Set by instruction
Condition for setting (WTIM0 = 1)
• Set by instruction
Condition for setting (ACKE0 = 1)
• Set by instruction
CHAPTER 15 SERIAL INTERFACE IICA
494