UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 446

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
(8) Interrupt request flag (ADIF)
(9) Conversion results just after A/D conversion start
(10) A/D conversion result register (ADCR, ADCRL, ADCRH) read operation
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is
changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-
change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time, when
ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-change
analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed.
Remarks 1. n = 0 to 10 (it depends on products)
The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS
bit is set to 1 within 1
measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result.
When a write operation is performed to the A/D converter mode register 0 (ADM0), analog input channel specification
register (ADS), and A/D port configuration registers 0, 1 (ADPC0, ADPC1), the contents of ADCR, ADCRL, and
ADCRH may become undefined. Read the conversion result following conversion completion before writing to ADM0,
ADS, ADPC0, and ADPC1. Using a timing other than the above may cause an incorrect conversion result to be read.
A/D conversion
ADCRL,
ADCRH
ADCR,
2. m = 0 to 10 (it depends on products)
ADIF
ADS rewrite
(start of ANIn conversion)
Figure 12-23. Timing of A/D Conversion End Interrupt Request Generation
μ
s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take
ANIn
ADS rewrite
(start of ANIm conversion)
ANIn
ANIn
ANIm
ANIn
ADIF is set but ANIm conversion
has not ended.
CHAPTER 12 A/D CONVERTER
ANIm
ANIm
ANIm
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