UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 85

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
(2) CALLT instruction table area
(3) Option byte area
(4) On-chip debug security ID setting area
(5) CALLF instruction entry area
3.1.2 Internal data memory space
(1) Internal high-speed RAM
3.1.3 Special function register (SFR) area
Tables 3-6 to 3-9 Special Function Register List in 3.2.3 Special function registers (SFRs)).
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
78K0/Kx2-L microcontrollers incorporate the following RAMs.
On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (refer to
Caution Do not access addresses to which SFRs are not assigned.
The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).
A 5-byte area of 0080H to 0084H and 1080H to 1084H can be used as an option byte area. Set the option byte at
0080H to 0084H when the boot swap is not used, and at 0080H to 0084H and 1080H to 1084H when the boot swap is
used. For details, refer to CHAPTER 24 OPTION BYTE.
A 10-byte area of 0085H to 008EH and 1085H to 108EH can be used as an on-chip debug security ID setting area.
Set the on-chip debug security ID of 10 bytes at 0085H to 008EH when the boot swap is not used and at 0085H to
008EH and 1085H to 108EH when the boot swap is used. For details, refer to CHAPTER 26 ON-CHIP DEBUG
FUNCTION.
The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit
registers per bank.
This area cannot be used as a program area in which instructions are written and executed.
The internal high-speed RAM can also be used as a stack memory.
μ
78F0555
μ
78F0556
μ
78F0557
PD78F0550,
PD78F0551,
PD78F0552,
78K0/KY2-L
−
μ
78F0565
μ
78F0566
μ
78F0567
PD78F0560,
PD78F0561,
PD78F0562,
78K0/KA2-L
Table 3-5. Internal High-Speed RAM Capacity
−
Product
μ
78F0576
μ
78F0577
μ
78F0578
PD78F0571,
PD78F0572,
PD78F0573,
78K0/KB2-L
−
μ
78F0586
μ
78F0587
μ
78F0588
PD78F0581,
PD78F0582,
PD78F0583,
78K0/KC2-L
−
CHAPTER 3 CPU ARCHITECTURE
384 × 8 bits
(FD80H to FEFFH)
512 × 8 bits
(FD00H to FEFFH)
768 × 8 bits
(FC00H to FEFFH)
1024 × 8 bits
(FB00H to FEFFH)
Internal High-Speed
RAM
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