UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 247

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
(4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has already
Caution
(5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D)
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Status Transition
(B) → (C) (X1 clock)
(B) → (C) (external main system clock)
Status Transition
(B) → (D) (XT1 clock)
(B) → (D) (external subsystem clock)
Remarks 1. (A) to (I) in Table 5-6 correspond to (A) to (I) in Figures 5-18 and 5-19.
Note 78K0/KC2-L only
been set.
Set the clock after the supply voltage has reached the operable voltage of the clock to be set (refer to
CHAPTER 28 ELECTRICAL SPECIFICATIONS).
2. EXCLK, OSCSEL, EXCLKS, OSCSELS:
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
MSTOP:
XSEL, MCM0:
XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC)
×:
Setting Flag of SFR Register
Setting Flag of SFR Register
Table 5-6. CPU Clock Transition and SFR Register Setting Examples (2/4)
Bits 7 to 4 of the clock operation mode select register (OSCCTL)
Bit 7 of the main OSC control register (MOC)
Bits 2 and 0 of the main clock mode register (MCM)
Don’t care
registers are already set
Unnecessary if these
EXCLK
XTSTART
0
1
0
1
0
Unnecessary if the CPU is operating
OSCSEL
1
1
with the subsystem clock
EXCLKS
0
×
1
Unnecessary if the CPU
MSTOP
is operating with the
high-speed system
0
0
OSCSELS
CHAPTER 5 CLOCK GENERATOR
clock
1
×
1
Must not be
Register
checked
Must be
checked
OSTC
Unnecessary
Stabilization
Waiting for
Necessary
Oscillation
XSEL
1
1
Note
Note
CSS
MCM0
1
1
1
1
233