UPD78F0551MA-FAA-AX Renesas Electronics America, UPD78F0551MA-FAA-AX Datasheet - Page 233

• Manufacturer Part Number: UPD78F0551MA-FAA-AX
• Description: MCU 8BIT 16-SSOP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2-Lr

Specifications of UPD78F0551MA-FAA-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 9
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2-L
R01UH0028EJ0400 Rev.4.00
Sep 27, 2010
Subsystem clock (f
Cautions 1.
Remark
<1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit.
(when XT1 oscillation
<2> When the power supply voltage exceeds 1.91 V (TYP.), the reset is released and the internal high-speed
<3> After the reset is released and reset processing is performed, the CPU starts operation on the internal high-speed
<4> Set the start of oscillation of the X1 or XT1 clock via software (refer to (1) in 5.6.1 Example of controlling high-
<5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
Internal high-speed
(when X1 oscillation
Internal reset signal
oscillation clock (f
system clock (f
Power supply
voltage (V
selected)
oscillator automatically starts oscillation.
oscillation clock.
speed system clock and (1) in 5.6.3 Example of controlling subsystem clock).
switching via software (refer to (3) in 5.6.1 Example of controlling high-speed system clock and (3) in 5.6.3
Example of controlling subsystem clock).
High-speed
CPU clock
selected)
2.
While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via software
settings.
executing the STOP instruction (refer to (4) in 5.6.1 Example of controlling high-speed system clock,
(3) in 5.6.2 Example of controlling internal high-speed oscillation clock, and (4) in 5.6.3 Example of
controlling subsystem clock).
Note 2
DD
SUB
0 V
XH
IH
Figure 5-17. Clock Generator Operation When Power Supply Voltage Is Turned On
)
If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application until the
voltage reaches 1.8 V, input a low level to the RESET pin from power application until the voltage
reaches 1.8 V, or set the LVI default start function enabled by using the option byte (LVISTART =
1) (refer to Figure 5-17). When a low level has been input to the RESET pin until the voltage
reaches 1.8 V, the CPU operates with the same timing as <2> and thereafter in Figure 5-16, after
the reset has been released by the RESET pin.
It is not necessary to wait for the oscillation stabilization time when an external clock input from
the EXCLK and EXCLKS pins is used.
)
)
)
(When LVI Default Start Function Enabled Is Set (Option Byte: LVISTART = 1))
<1>
The internal high-speed oscillation clock and high-speed system clock can be stopped by
Waiting for oscillation
accuracy stabilization
(102 to 407 s)
1.91 V (TYP.)
Starting X1 oscillation
is set by software.
<3>
<2>
Starting XT1 oscillation
is set by software.
<4>
oscillation stabilization time:
Reset processing (12 to 51 s)
<4>
Internal high-speed
oscillation clock
2
8
/f
X
X1 clock
to 2
18
/f
X
Note 1
CHAPTER 5 CLOCK GENERATOR
<5>
High-speed system clock
Switched by
software
<5>
Subsystem clock
Note 2
219