M37542F8FP Renesas Electronics America, M37542F8FP Datasheet - Page 122

• Manufacturer Part Number: M37542F8FP
• Description: IC 740 MCU FLASH 32K 36SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37542F8FP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Rev.
3.00 Jun 01, 2005
3.01 Nov 02, 2005
Date
REVISION HISTORY
114-122
Page
100
105
108
110
125
132
133
10
11
12
21
24
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53
54
60
63
72
73
77
86
87
91
92
95
98
57
61
1
2
3
5
-
-
ROM size of Flash memory version revised.
Fig.1 M37542F8GP → M37542FxGP
Fig.2 M37542F8FP → M37542FxFP
Fig.3 M37542F8SP → M37542FxSP
Table 1 Performance overview added.
Table 2 Function of Vcc, Vss revised.
Flash memory size revised, and Fig.10 M37542F4 added.
Table 3 M37542F4GP,M37542F4FP,M37542F4SP added.
Fig. 20 (5) Port P0
Table 7 Termination of unused pins added.
Description of Serial I/O revised.
[UART2 control register (UART2CON)] revised.
Fig. 64 UART2 contorl register revised.
Description of Clock Generating Circuit revised. Fig. 74 revised.
Fig. 79 revised.
Table 9 Temperature at program/erase added.
Fig.94 16 Kbyte ROM Product added.
Table 11 List of software commands (CPU rewrite mode) revised.
Fig.104 M37542F8GP → M37542FxGP
Fig.105 M37542F8SP → M37542FxSP
Fig.106 M37542F8FP → M37542FxFP
Fig.109 M37542F8GP → M37542FxGP
Fig.110 M37542F8SP → M37542FxSP
Fig.111 M37542F8FP → M37542FxFP
M37542F4GP,M37542F4FP,M37542F4SP added.
Table 15 Conditions: Description added.
Table 18 Note 1 added.
Table 20, Fig. 104 added.
Table 28 Conditions: Description added.
Table 31 Note 1 added.
Table 34, Fig. 106 added.
Extended operating temperature 125 °C version added.
(2) How to reference the processor status register revised.
Fig. 2 revised.
Package revised.
Bit name revised: STP instruction disable bit → STP instruction function selection bit
- Description for “Operation of STP instruction function selection bit” revised.
- Notes on Watchdog Timer added.
- Fig.68: Blodk diagram of watchdog timer revised.
- Fig.69: Bit 6 and Bit 7 of WDTCON revised.
-Notes on Clock Generating Circuit : Note on Count source added.
Notes on Watchdog Timer : Note on Count source added.
Notes on Clock Generating Circuit : Note on Count source added.
→ STP instruction function selection bit
Bit 6: Bit name and its description revised. (Bit function is not changed.)
0 : System enters into the stop mode at the STP instruction execution
1 : Internal reset occurs at the STP instruction execution
5
revised.
A - 3
Description
Summary
7542 Group Datasheet