M37542F8FP Renesas Electronics America, M37542F8FP Datasheet - Page 39

• Manufacturer Part Number: M37542F8FP
• Description: IC 740 MCU FLASH 32K 36SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37542F8FP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Fig. 38 Structure of timer source selection register
7542 Group
Rev.3.03
REJ03B0006-0303
Fig. 37 Structure of capture/compare port register
Fig. 39 Structure of compare output mode register
b 7
b 7
b 7
Jul 11, 2008
b 0
C a p t u r e / C o m p a r e p o r t r e g i s t e r
( C C P R : a d d r e s s 0 0 1 E
b 0
C a p t u r e 0 i n p u t p o r t b i t s
C o m p a r e 0 o u t p u t p o r t b i t
0 : P 0
1 : P 0
C o m p a r e 1 o u t p u t p o r t b i t
0 : P 0
1 : P 0
C a p t u r e 1 i n p u t p o r t b i t
0 : C a p t u r e f r o m P 3
1 : R i n g / 5 1 2
C o m p a r e 2 o u t p u t p o r t b i t
0 : P 3
1 : P 3
C o m p a r e 3 o u t p u t p o r t b i t
0 : P 3
1 : P 3
N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d )
b 0
b 1 b 0
0 0 : C a p t u r e f r o m P 0
0 1 : C a p t u r e f r o m P 1
1 0 : R i n g / 5 1 2
1 1 : N o t a v a i l a b l e
T i m e r s o u r c e s e l e c t i o n r e g i s t e r
( T M S R : a d d r e s s 0 0 1 F
C o m p a r e o u t p u t m o d e r e g i s t e r
( C M O M : a d d r e s s 0 0 2 1
C o m p a r e 0 t i m e r s o u r c e b i t
C o m p a r e 1 t i m e r s o u r c e b i t
C o m p a r e 2 t i m e r s o u r c e b i t
C o m p a r e 3 t i m e r s o u r c e b i t
C a p t u r e 0 t i m e r s o u r c e b i t
C a p t u r e 1 t i m e r s o u r c e b i t
N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d )
0 : T i m e r A
1 : T i m e r B
1
1
2
2
1
1
2
2
C o m p a r e 0 o u t p u t l e v e l l a t c h
0 : P o s i t i v e
1 : N e g a t i v e
C o m p a r e 1 o u t p u t l e v e l l a t c h
0 : P o s i t i v e
1 : N e g a t i v e
C o m p a r e 2 o u t p u t l e v e l l a t c h
0 : P o s i t i v e
1 : N e g a t i v e
C o m p a r e 3 o u t p u t l e v e l l a t c h
0 : P o s i t i v e
1 : N e g a t i v e
C o m p a r e 0 t r i g g e r e n a b l e b i t
0 : D i s a b l e d
1 : E n a b l e d
C o m p a r e 1 t r i g g e r e n a b l e b i t
0 : D i s a b l e d
1 : E n a b l e d
C o m p a r e 2 t r i g g e r e n a b l e b i t
0 : D i s a b l e d
1 : E n a b l e d
C o m p a r e 3 t r i g g e r e n a b l e b i t
0 : D i s a b l e d
1 : E n a b l e d
i s I / O p o r t
i s C o m p a r e 0
i s I / O p o r t
i s C o m p a r e 1
i s I / O p o r t
i s C o m p a r e 2
i s I / O p o r t
i s C o m p a r e 3
Page 37 of 117
0
1 6
, i n i t i a l v a l u e : 0 0
0
0
1 6
1 6
, i n i t i a l v a l u e : 0 0
, i n i t i a l v a l u e : 0 0
1 6
)
1 6
1 6
)
)
Fig. 41 Structure of compare interrupt source register
Fig. 40 Structure of capture/compare status register
b 7
b 7
b 0
b 0
C o m p a r e i n t e r r u p t s o u r c e s e t r e g i s t e r
( C I S R : a d d r e s s 0 0 2 3
C a p t u r e / C o m p a r e s t a t u s r e g i s t e r
( C C S R : a d d r e s s 0 0 2 2
C o m p a r e l a t c h 0 0 i n t e r r u p t s o u r c e b i t
C o m p a r e l a t c h 0 1 i n t e r r u p t s o u r c e b i t
C o m p a r e l a t c h 1 0 i n t e r r u p t s o u r c e b i t
C o m p a r e l a t c h 1 1 i n t e r r u p t s o u r c e b i t
C o m p a r e l a t c h 2 0 i n t e r r u p t s o u r c e b i t
C o m p a r e l a t c h 2 1 i n t e r r u p t s o u r c e b i t
C o m p a r e l a t c h 3 0 i n t e r r u p t s o u r c e b i t
C o m p a r e l a t c h 3 1 i n t e r r u p t s o u r c e b i t
0 : D i s a b l e d
1 : E n a b l e d
C o m p a r e 0 o u t p u t s t a t u s b i t
0 : “ L ” l e v e l o u t p u t
1 : “ H ” l e v e l o u t p u t
C o m p a r e 1 o u t p u t s t a t u s b i t
0 : “ L ” l e v e l o u t p u t
1 : “ H ” l e v e l o u t p u t
C o m p a r e 2 o u t p u t s t a t u s b i t
0 : “ L ” l e v e l o u t p u t
1 : “ H ” l e v e l o u t p u t
C o m p a r e 3 o u t p u t s t a t u s b i t
0 : “ L ” l e v e l o u t p u t
1 : “ H ” l e v e l o u t p u t
C a p t u r e 0 s t a t u s b i t
0 : l a t c h 0 0 c a p t u r e d
1 : l a t c h 0 1 c a p t u r e d
C a p t u r e 1 s t a t u s b i t
0 : l a t c h 1 0 c a p t u r e d
1 : l a t c h 1 1 c a p t u r e d
N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d )
1 6
1 6
, i n i t i a l v a l u e : 0 0
, i n i t i a l v a l u e : 0 0
1 6
1 6
)
)