M37542F8FP Renesas Electronics America, M37542F8FP Datasheet - Page 38

• Manufacturer Part Number: M37542F8FP
• Description: IC 740 MCU FLASH 32K 36SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37542F8FP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7542 Group
Output compare
7542 group has 4-output compare channels. Each channel (0 to 3)
has the same function and can be used to output waveform by us-
ing count value of either Timer A or Timer B.
The source timer for each channel is selected by setting value of
the compare x (x = 0, 1, 2, 3) timer source bit. Timer A and Timer B
can be selected for the source timer to each channel, respectively.
To use each compare channel, set “1” to the compare x output
port bit and set the port direction register corresponding to com-
pare channel to output mode.
The compare value for each channel is set to the compare regis-
ter (low-order) and compare register (high-order).
Writing to the register for each channel is controlled by setting
value of compare register write pointer. Writing to each register is
in the following order;
1.Set the value of corresponded output compare channel to the
2.Write a value to the compare register (low-order) and compare
3.Set “1” to the compare latch y (y = 00, 01, 10, 11, 20, 21, 30, 31)
When count value of timer and setting value of compare latch is
matched, compare output trigger occurs.
When “1: Enabled” is set to the compare trigger x enable bit, the
output waveform from port is inverted by compare trigger.
When “0: Disabled” is set to the compare trigger x enable bit, the out-
put waveform is not inverted, so port output can be fixed to “H” or “L”.
When “0: Positive” is set to the compare x output level latch, the
compare output waveform is turned to “H level” at compare latch
x0’s match and turned to “L level” at compare latch x1’s match.
When “1 :Negative” is set to the compare x output level latch, the
compare output waveform is turned to “L level” at compare latch
x0’s match and turned to “H level” at compare latch x1’s match.
The compare output level of each channel can be confirmed by
reading the compare x output status bit.
Compare output interrupt is available when match of each com-
pare channel and timer count value. The interrupt request from
each channel can be disabled or enabled by setting value of com-
pare latch y interrupt source bit.
Compare 0,1 (2,3) modulation mode
In compare modulation mode, modulation waveform can be gener-
ated by using compare channel 0 and 1, or compare channel 2 and 3.
To use this mode,
• Set “1: Enabled” to the compare 0,1 (2, 3) modulation mode bit.
• Set Timer A underflow for Timer B count source.
• Set Timer A for the timer source of compare channel 0 (2).
• Set Timer B for the timer source of compare channel 1 (3).
In this mode, AND waveform of compare 0 (1) and compare 2 (3)
is generated from Port P0
order to use this mode, set “1” to the compare 0 output port bit or
compare 2 output port bit.
Rev.3.03
REJ03B0006-0303
compare register write pointer.
register (high-order).
re-load bit.
When “1” is set to the compare latch y re-load bit, the value set
to the compare register is loaded to compare latch when the
next timer underflow.
Jul 11, 2008
1
and P3
Page 36 of 117
1
, respectively. Accordingly, in
• When the selected source timer of each compare channel is
• Do not write the same data to both of compare latch x0 and x1.
• When setting value of the compare latch is larger than timer set-
• When the compare x trigger enable bit is cleared to “0” (dis-
Fig. 35 Structure of capture/compare register R/W pointer
Fig. 36 Structure of compare register re-load register
stopped, written data to compare register is loaded to the com-
pare latch simultaneously.
ting value, compare match signal is not generated. Accordingly,
the output waveform is fixed to “L” or “H” level.
However, when setting value of another compare latch is
smaller than timer setting value, this compare match signal is
generated. Accordingly, compare match interrupt occurs.
abled), the match trigger to the waveform output circuit is
disabled, and the output waveform can be fixed to “L” or “H”
level.
However, in this case, the compare match signal is generated.
Accordingly, compare match interrupt occurs.
Notes on Output Compare
b 7
b 7
b 0
b 0
C o m p a r e r e g i s t e r r e - l o a d r e g i s t e r
( C M P R : a d d r e s s 0 0 1 4
C a p t u r e / c o m p a r e r e g i s t e r R / W p o i n t e r
( C C R P : a d d r e s s 0 0 1 2
C o m p a r e l a t c h 0 0 , 0 1 r e - l o a d b i t
0 : R e - l o a d d i s a b l e d
1 : R e - l o a d a t n e x t u n d e r f l o w
C o m p a r e l a t c h 1 0 , 1 1 r e - l o a d b i t
0 : R e - l o a d d i s a b l e d
1 : R e - l o a d a t n e x t u n d e r f l o w
C o m p a r e l a t c h 2 0 , 2 1 r e - l o a d b i t
0 : R e - l o a d d i s a b l e d
1 : R e - l o a d a t n e x t u n d e r f l o w
C o m p a r e l a t c h 3 0 , 3 1 r e - l o a d b i t
0 : R e - l o a d d i s a b l e d
1 : R e - l o a d a t n e x t u n d e r f l o w
N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d )
C o m p a r e r e g i s t e r R / W p o i n t e r
N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d )
C a p t u r e r e g i s t e r 0 R / W p o i n t e r
0 : C a p t u r e l a t c h 0 0
1 : C a p t u r e l a t c h 0 1
C a p t u r e r e g i s t e r 1 R / W p o i n t e r
0 : C a p t u r e l a t c h 1 0
1 : C a p t u r e l a t c h 1 1
N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d )
b 2 b 1 b 0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : C o m p a r e l a t c h 0 0
1 : C o m p a r e l a t c h 0 1
0 : C o m p a r e l a t c h 1 0
1 : C o m p a r e l a t c h 1 1
0 : C o m p a r e l a t c h 2 0
1 : C o m p a r e l a t c h 2 1
0 : C o m p a r e l a t c h 3 0
1 : C o m p a r e l a t c h 3 1
1 6
1 6
, i n i t i a l v a l u e : 0 0
, i n i t i a l v a l u e : 0 0
1 6
1 6
)
)