M37542F8FP Renesas Electronics America, M37542F8FP Datasheet - Page 78

• Manufacturer Part Number: M37542F8FP
• Description: IC 740 MCU FLASH 32K 36SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37542F8FP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Figure 99 shows the flash memory control register 1.
Bit 0 of the flash memory control register 1 is the Erase suspend
enable bit. By setting this bit to “1”, the erase suspend mode to
suspend erase processing temporarily when block erase com-
mand is executed can be used. In order to set this bit to “1”,
writing “0” and “1” in succession to bit 0. In order to set this bit to
“0”, write “0” only to bit 0.
Bit 1 of the flash memory control register 1 is the erase suspend
request bit. By setting this bit to “1” when erase suspend enable
bit is “1”, the erase processing is suspended.
Bit 6 of the flash memory control register 1 is the erase suspend
flag. This bit is cleared to “0” at the flash erasing.
Figure 100 shows the flash memory control register 2.
Bit 0 of the flash memory control register 1 is the all user block E/
W enable bit. By setting this bit to “0”, Erase/Write to all user block
(blocks 0, 1, 2) is disabled. As a result, error writing in program to
write only to data block can be prevented.
7542 Group
Table 10 Erase/Write disable setting
Rev.3.03
REJ03B0006-0303
mode select bit
CPU rewrite
0
0
0
0
1
1
1
1
Jul 11, 2008
E/W enable bit
All user block
0
0
1
1
0
0
1
1
Page 76 of 117
8KB user block
E/W enable bit
0
1
0
1
0
1
0
1
E/W disabled (RESET)
E/W disabled
E/W disabled
E/W disabled
E/W disabled
E/W disabled
E/W disabled
Block 0: 8KB
Block 1: 8KB
E/W enabled
Fig. 100 Structure of flash memory control register 2
Fig. 99 Structure of flash memory control register 1
b7
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
b7
2: Effective only when the suspend enable bit = “1”.
2: Effective only when the CPU rewrite mode select bit = “1”.
“1” to it in succession. For this bit to be set to “0”, write “0” only to
this bit.
“1” to it in succession. For this bit to be set to “0”, write “0” only to
this bit.
E/W disabled (RESET)
Block 2: 16KB
E/W disabled
E/W disabled
E/W disabled
E/W disabled
E/W disabled
E/W enabled
E/W enabled
b0
b0
Flash memory control register 1
(FMCR1: address : 0FE1
Erase Suspend enble bit (Notes 1)
0 : Suspend invalid
1 : Suspend valid
Erase Suspend
0 : Erase restart
1 : Suspend request
Not used (do not write “1” to this bit.)
Erase Suspend flag
0 :
1 :
Not used (do not write “1” to this bit.)
Reserved bit (returns “1” when read)
Reserved bits (do not write “1” to this bit.)
All user block E/W enable
0 : E/W disabled
1 : E/W enabled
Not used (do not write “1” to this bit.)
Flash memory control register 2
(FMCR2: address : 0FE2
Erase
Erase
active
inactive (Erase Suspend mode)
request bit
E/W disabled (RESET)
16
Data block B: 2KB
Data block A: 2KB
: initial value: 40
(Notes 2)
16
bit
E/W disabled
E/W disabled
E/W disabled
E/W enabled
E/W enabled
E/W enabled
E/W enabled
: initial value: 01
(Notes 1, 2)
16
)
16
)