M37542F8FP Renesas Electronics America, M37542F8FP Datasheet - Page 67

• Manufacturer Part Number: M37542F8FP
• Description: IC 740 MCU FLASH 32K 36SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37542F8FP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7542 Group
Rev.3.03
REJ03B0006-0303
Fig. 84 State transition
f(X
On-chip oscillator: stop
Operation clock source: f(X
Notes on switch of clock
(1) In operation clock = f(X
(2) In operation clock = On-chip oscillator, the following can be selected for the CPU clock division ratio.
(3) After system is released from reset, and state transition of state 2 → state 3 and state transition of state 2’ → state 3’,
(4) Executing the state transition state 3 to 2 or state 3 to 3’ after stabilizing X
(5) When the state 2 → state 3 → state 4 is performed, execute the NOP instruction as shown below
(6) When the state 3 → state 2 → state 1 is performed, execute the NOP instruction as shown below
IN
WAIT mode 1
Interrupt
) oscillation: enabled
f(X
f(X
f(X
R
R
R
R
R
according to the division ratio of CPU clock.
1. CPUM
2. NOP instruction
3. CPU
according to the division ratio of CPU clock.
1. CPUM
2. NOP instruction
3. CPUM
OSC
OSC
OSC
OSC
OSC
Transition from Double-speed mode: NOP
Transition from High-speed mode: NOP
Transition from Middle-speed mode: NOP
Transition from On-chip oscillator double-speed mode: NOP
Transition from On-chip oscillator high-speed mode: NOP
Transition from On-chip oscillator middle-speed mode: NOP
Transition from On-chip oscillator low-speed mode: NOP
IN
IN
IN
State 1
Jul 11, 2008
)/2 (high-speed mode)
)/8 (middle-speed mode)
) (double-speed mode, only at a ceramic oscillation)
/8 (On-chip oscillator middle-speed mode) is selected for CPU clock.
/1 (On-chip oscillator double-speed mode)
/2 (On-chip oscillator high-speed mode)
/8 (On-chip oscillator middle-speed mode)
/128 (On-chip oscillator low-speed mode)
4
= 1
WIT
instruction
76
76
3
= 1
= 10
= 00
2
(state 3 → state 4)
2
(state 2 → state 1)
2
2
(state 2 → state 3)
or 01
CPUM
CPUM
IN
2
), the following can be selected for the CPU clock division ratio.
or 11
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Interrupt
3
3
=0
=1
2
2
IN
2
) (Note 1)
(state 3 → state 2)
f(X
On-chip oscillator: enabled
f(X
On-chip oscillator: enabled
Oscillation stop detection circuit valid
WIT
instruction
MISRG
WAIT mode 2
IN
WAIT mode 2’
IN
Interrupt
) oscillation: enabled
) oscillation: enabled
STP
instruction
1
State 2’
State 2
=1
2
1
WIT
instruction
MISRG
Interrupt
0
3
Interrupt
1
=0
2
STP mode
f(X
On-chip oscillator: stop
STP
instruction
IN
CPUM
CPUM
CPUM
(Note 3)
CPUM
(Note 3)
) oscillation: stop
0
2
Interrupt
(Note 4)
0
76
76
4
76
76
=00
=00
=10
=10
01
01
11
11
2
2
2
2
2
2
2
2
STP
instruction
IN
f(X
On-chip oscillator: enabled
f(X
On-chip oscillator: enabled
Operation clock source: On-chip oscillator (Note 2)
WIT
instruction
MISRG
(Note 4)
WAIT mode 3’
oscillation.
WAIT mode 3
IN
IN
Interrupt
) oscillation: enabled
) oscillation: enabled
State 3’
1
State 3
=1
2
Interrupt
MISRG
Interrupt
WIT
instruction
1
=0
2
STP
instruction
CPUM
CPUM
4
4
=0
=1
2
2
f(X
On-chip oscillator: enabled
RESET state
f(X
On-chip oscillator: enabled
Reset
released
(Note 3)
IN
WAIT mode 4
IN
Interrupt
) oscillation: stop
) oscillation: enabled
State 4
WIT
instruction