M37542F8FP Renesas Electronics America, M37542F8FP Datasheet - Page 84

• Manufacturer Part Number: M37542F8FP
• Description: IC 740 MCU FLASH 32K 36SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37542F8FP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7542 Group
Memory Version
To prevent the contents of internal flash memory from being read
out or rewritten easily, this MCU incorporates a ROM code protect
function for use in parallel I/O mode and an ID code check func-
tion for use in standard serial I/O mode.
(1) ROM Code Protect Function
The ROM code protect function is the function to inhibit reading
out or modifying the contents of internal flash memory by using
the ROM code protect control address (address FFDB
lel I/O mode. Figure 105 shows the ROM code protect control
address (address FFDB
area.)
Fig. 105 Structure of ROM code protect control address
Rev.3.03
REJ03B0006-0303
Functions To Inhibit Rewriting Flash
Jul 11, 2008
b 7
N o t e s 1: W h e n R O M c o d e p r o t e c t i s t u r n e d o n , t h e i n t e r n a l f l a s h m e m o r y i s p r o t e c t e d
2: W h e n R O M c o d e p r o t e c t l e v e l 2 i s t u r n e d o n , R O M c o d e r e a d o u t b y a s h i p m e n t
3: T h e R O M c o d e p r o t e c t r e s e t b i t s c a n b e u s e d t o t u r n o f f R O M c o d e p r o t e c t l e v e l 1
16
). (This address exists in the User ROM
a g a i n s t r e a d o u t o r m o d i f i c a t i o n i n p a r a l l e l I / O m o d e .
i n s p e c t i o n L S I t e s t e r , e t c . a l s o i s i n h i b i t e d .
a n d R O M c o d e p r o t e c t l e v e l 2 . H o w e v e r , s i n c e t h e s e b i t s c a n n o t b e m o d i f i e d i n
p a r a l l e l I / O m o d e , t h e y n e e d t o b e r e w r i t t e n i n s e r i a l I / O m o d e o r C P U r e w r i t e
m o d e .
Page 82 of 117
1 1
b 0
R O M c o d e p r o t e c t c o n t r o l a d d r e s s ( a d d r e s s F F D B
R O M C P ( F F
16
Reserved bits (“1” at read/write)
ROM code protect level 2 set bits (ROMCP2) (Notes 1, 2)
ROM code protect reset bits (Note 3)
ROM code protect level 1 set bits (ROMCP1) (Note 1)
) in paral-
b3b2
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
b5b4
0 0: Protect removed
0 1: Protect set bits effective
1 0: Protect set bits effective
1 1: Protect set bits effective
b7b6
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
1 6
w h e n s h i p p e d )
If one or both of the pair of ROM code protect bits is set to “0”, the
ROM code protect is turned on, so that the contents of internal
flash memory are protected against readout and modification. The
ROM code protect is implemented in two levels. If level 2 is se-
lected, the flash memory is protected even against readout by a
shipment inspection LSI tester, etc. When an attempt is made to
select both level 1 and level 2, level 2 is selected by default.
If both of the two ROM code protect reset bits are set to “00”, the
ROM code protect is turned off, so that the contents of internal
flash memory can be readout or modified. Once the ROM code
protect is turned on, the contents of the ROM code protect reset
bits cannot be modified in parallel I/O mode. Use the serial I/O or
CPU rewrite mode to rewrite the contents of the ROM code protect
reset bits.
Rewriting of only the ROM code protect control address (address
FFDB
tect reset bit, rewrite the whole user ROM area (block 0)
containing the ROM code protect control address.
16
) cannot be performed. When rewriting the ROM code pro-
1 6
)