M37542F8FP Renesas Electronics America, M37542F8FP Datasheet - Page 28

• Manufacturer Part Number: M37542F8FP
• Description: IC 740 MCU FLASH 32K 36SSOP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M37542F8FP

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SIO, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 36-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7542 Group
Fig. 23 Interrupt control
• Interrupt Disable Flag
The interrupt disable flag is assigned to bit 2 of the processor sta-
tus register. This flag controls the acceptance of all interrupt
requests except for the BRK instruction. When this flag is set to
“1”, the acceptance of interrupt requests is disabled. When it is set
to “0”, the acceptance of interrupt requests is enabled. This flag is
set to “1” with the SEI instruction and set to “0” with the CLI in-
struction.
When an interrupt request is accepted, the contents of the proces-
sor status register are pushed onto the stack while the interrupt
disable flag remains set to “0”. Subsequently, this flag is automati-
cally set to “1” and multiple interrupts are disabled.
To use multiple interrupts, set this flag to “0” with the CLI instruc-
tion within the interrupt processing routine.
The contents of the processor status register are popped off the
stack with the RTI instruction.
• Interrupt Request Bits
Once an interrupt request is generated, the corresponding inter-
rupt request bit is set to “1” and remains “1” until the request is
accepted. When the request is accepted, this bit is automatically
set to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to
“1”, by software.
• Interrupt Enable Bits
The interrupt enable bits control the acceptance of the corre-
sponding interrupt requests. When an interrupt enable bit is set to
“0”, the acceptance of the corresponding interrupt request is dis-
abled. If an interrupt request occurs in this condition, the
corresponding interrupt request bit is set to “1”, but the interrupt
request is not accepted. When an interrupt enable bit is set to “1”,
the acceptance of the corresponding interrupt request is enabled.
Each interrupt enable bit can be set to “0” or “1” by software.
The interrupt enable bit for an unused interrupt should be set to
“0”.
Rev.3.03
REJ03B0006-0303
Interrupt request bit
Interrupt enable bit
Jul 11, 2008
Interrupt disable flag I
Page 26 of 117
BRK instruction
Reset
• Interrupt Enable Setting
The following interrupt sources can be set to valid or invalid by the
interrupt source set register (000A
• External Interrupt Pin Selection
For the external interrupt INT
can be selected by the INT
edge selection register (bit 2 of address 003A
However, since there is no P3
PWQN0036KA-A package, select P3
wakeup selection bit, enable/disable of a key-on wakeup of P0
P0
• Key-on wakeup
• UART1 bus collision detection interrupt
• A/D conversion
• Timer 1 interrupt
4
, and P0
6
pins can be selected, respectively.
1
input port selection bit in the interrupt
1
, the external input pin P3
Interrupt acceptance
6
/INT
16
).
1
3
pin in the 32-pin version
/INT
1
16
pin. By the key-on
).
3
or P3
0
6
,