MC68HC908LB8CPE Freescale Semiconductor, MC68HC908LB8CPE Datasheet - Page 106

• Manufacturer Part Number: MC68HC908LB8CPE
• Description: IC MCU 8K FLASH 8MHZ 20DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908LB8CPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVR, POR, PWM
• Number Of I /o: 18
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -

High Resolution PWM (HRP)
HRPMODE — Mode Select
HRPEN — Enable
When the HRP is disabled the TOP and BOT outputs both switch to logic 0. If a logic 0 is detected on the
SHTDWN input pin, the module outputs both switch to logic 0 and the HRPEN bit is automatically set to 0
to disable the module.
10.8.2 HRP Duty Cycle Registers
The two read/write duty cycle registers contain the 16-bit duty cycle of the output after dithering. It is split
into two parts:
The duty cycle including dithering in variable duty cycle mode is:
where 2
HRPDCH:HRPDCL are not used in variable frequency mode. The contents of the registers have no effect
in this mode
Writes to the high byte (HRPDCH) are stored in a latch until the low byte (HRPDCL) is written. Both
registers are then updated simultaneously. This prevents glitches in the output duty cycle.
106
1. 11-bit duty cycle value (DC[10:0]) used to generate the HRP output waveforms.
2. 5-bit step value (STEP[4:0]) that defines the percentage of time spent on the larger of two duty
This read/write bit enables the SHTDWN functionality on pin PTC2/SHTDWN/IRQ. When SHTDWN
functionality is enabled, a falling edge or a low level on the SHTDWN pin causes the TOP and BOT
outputs to be switched to logic 0 and the HRPEN bit is set to logic 0, disabling the HRP.
This read/write bit selects between variable frequency and variable duty cycle modes of operation.
This read/write bit enables/disables the HRP.
1 = Pin PTC2/SHTDWN/IRQ functions as SHTDWN input.
0 = Pin PTC2/SHTDWN/IRQ functions controlled by port C register
1 = Variable duty cycle mode
0 = Variable frequency mode
1 = HRP enabled
0 = HRP disabled
cycle values in variable duty cycle mode.
SEL[2:0]
The TOP and BOT pins must be enabled using the HRPOE bit for the
HRPEN bit to have any effect on the PTB0/TOP and PTB1/BOT I/O pins.
The TOP and BOT pins must be enabled using the HRPOE bit for the
HRPEN bit to have any effect on the PTB0/TOP and PTB1/BOT I/O pins.
is the STEP[4:0] scaling factor.
Output Duty Cycle
MC68HC908LB8 Data Sheet, Rev. 1
=
DC 10:0
-------------------------
HRPCLK
[
NOTE
NOTE
]
+
------------------------------------------------- -
------------------ -
2
INT
SEL[2:0]
32
⎛
⎝
STEP 4:0
---------------------------- -
2
¥
SEL[2:0]
HRPCLK
[
]
⎞
⎠
Freescale Semiconductor
(EQ 10-11)