MC68HC908LB8CPE Freescale Semiconductor, MC68HC908LB8CPE Datasheet - Page 193
MC68HC908LB8CPE
Manufacturer Part Number
MC68HC908LB8CPE
Description
IC MCU 8K FLASH 8MHZ 20DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68HC908LB8CDWE.pdf
(234 pages)
Specifications of MC68HC908LB8CPE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVR, POR, PWM
Number Of I /o
18
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 7x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
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Manufacturer
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18.3.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following
initialization procedure:
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel
0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0
(TSCR0) controls and monitors the PWM signal from the linked channels.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty
cycle output. See
18.4 Interrupts
The following TIM sources can generate interrupt requests:
Freescale Semiconductor
1. In the TIM status and control register (TSC):
2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width.
4. In TIM channel x status and control register (TSCx):
5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
period.
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST.
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level
or PWM signals) to the mode select bits, MSxB:MSxA. See
select bits, ELSxB:ELSxA. The output action on compare must force the output to the
complement of the pulse width level. See
In buffered PWM signal generation, do not write new pulse width values to
the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as generating
unbuffered PWM signals.
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
18.8.4 TIM Channel Status and Control
MC68HC908LB8 Data Sheet, Rev. 1
NOTE
NOTE
Table
Registers.
18-2.
Table
18-2.
Interrupts
193
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